sb0_ changed the topic of #m-labs to: https://m-labs.hk :: Logs http://irclog.whitequark.org/m-labs
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<xobs> Hi, I'm trying to debug a FSM. Is Migen's FSM object documented anywhere? Also, how can I output the current state to some pins, so I can monitor it with an LA?
<xobs> Or is there no way to get the state, and I just have to manually set signals as I enter and leave states?
<kay2> xobs: why don't you do it in simulation first ?
<xobs> kay2: this particular design works fine in simulation, but behaves oddly on real hardware.
<kay2> rarely happen ;)
<kay2> you have fsm.state then in this case
<kay2> you are using a SoC ?
<xobs> I am.
<kay2> misoc or litex ?
<xobs> When I tried that, Python said "AttributeError: 'FSM' object has no attribute 'state"
<xobs> Litex
<kay2> then concider using litescope
<xobs> I don't think I have enough room on this FPGA to add in litescope. It's 90% full already...
<kay2> xobs: maybe it's there in the finalize ?
<kay2> what fpga is it ?
<xobs> IC40UP5K
<kay2> state exists once finalized
<kay2> xobs: and adding a signal yourself would end up doing https://github.com/m-labs/migen/blob/master/migen/genlib/fsm.py#L175
<xobs> What does "finalized" mean? Should I call `do_finalize()` myself on the FSM in order to access the state?
<kay2> migen does it on 2nd pass
<xobs> Is the FSM documented anywhere? I just see documentation on `FSM.act()`, but I see a lot more functions used. For example, what does NextValue() do?
<kay2> allows you to synchroniously set a value
<kay2> what are you trying to do with this fsm ?
<xobs> I understand that it sets a particular Signal to a given Value. Does that only happen for the next clock cycle? Or does it permanently change the value and it goes back to 0 in two cycles? Or does it set the value and keep it there until it's transitioned to another state?
<kay2> it does set the value synchroniously !
<kay2> as if you were in a self.sync
<kay2> while the rest of the fsm is done in comb
<kay2> try to explain more what you are trying to achieve with ur fsm
<xobs> I'm trying to get a USB stack working.
<xobs> There are two shift registers: One for Tx and one for Rx. I can transmit data just fine, and I can receive data just fine, and this state machine that glues them together works fine in simulation, but gives random and corrupt values during execution on real hardware.
<xobs> I'm trying to understand whether it's getting into a bad state due to some async logic bugs, or maybe it's just skipping states altogether.
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<kay2> hard to tell
<xobs> Yeah, I really think I'm not understanding what a Migen FSM is. I brought out one particular state to an external pin, and I'm seeing that it spends 4ns in this state. That... is probably the source of my problems.
<xobs> Are before/after_entering/leaving() documented anywhere?
<kay2> in the example?
<kay2> what usb core are you using ? valentyusb ?
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<xobs> Yeah, I'm porting valentyusb to Fomu.
<kay2> i thought mitro was doing that
<xobs> I took it over from him.
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