06:49 <lkcl> has anyone written any co-routine infrastructure for unit testing or simulations?

06:51 <lkcl> i have a rather complex multi-input multiplexer with multiple STB/BSY signals, which would be flat-out impossible to understand if it was written as a single linear unit test

07:39 <lkcl> i figured on doing something which took an array of functions and performed a "yield" on each, in turn, requiring that each yield a single clock (empty yield) before allowing the loop to proceed

07:39 <lkcl> that way each co-routine will be clock-synchronised

07:41 <lkcl> then it will be possible to have a co-routine for each input, looking for BUSY signals and acknowledging them, placing data on the input and setting STB accordingly.

07:54 <bb-m-labs> build #2961 of artiq is complete: Failure [failed python_unittest_1] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2961 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>

16:38 <bb-m-labs> build #2483 of artiq-board is complete: Failure [failed conda_build] Build details are at http://buildbot.m-labs.hk/builders/artiq-board/builds/2483 blamelist: Chris Ballance <chris.ballance@physics.ox.ac.uk>

16:38 <bb-m-labs> build #2962 of artiq is complete: Failure [failed anaconda_upload] Build details are at http://buildbot.m-labs.hk/builders/artiq/builds/2962 blamelist: Chris Ballance <chris.ballance@physics.ox.ac.uk>