03:18 <d_n|a> bb-m-labs: force build --branch=pull/1299/head artiq

03:18 <bb-m-labs> build #2978 forced

03:18 <bb-m-labs> I'll give a shout when the build finishes

03:37 <d_n|a> whitequark: See PRs 1299/1300 regarding the escape analysis issue discussed earlier, and a (seemingly) obvious improvement in quoting tuples. I'll merge once green unless you have any objections.

03:47 <bb-m-labs> build #2499 of artiq-board is complete: Success [build successful] Build details are at https://buildbot.m-labs.hk/builders/artiq-board/builds/2499

03:49 <bb-m-labs> build #2978 of artiq is complete: Failure [failed set_log_level] Build details are at https://buildbot.m-labs.hk/builders/artiq/builds/2978

12:55 <d_n|a> bb-m-labs: force build --branch=pull/1300/head artiq

12:55 <bb-m-labs> build #2979 forced

12:55 <bb-m-labs> I'll give a shout when the build finishes

13:04 <d_n|a> sb0: Any idea what's going on with the above set_log_level buildbot failures? The ping step succeeds, and locally a firmware build with the changes appears functional

13:06 <bb-m-labs> build #2979 of artiq is complete: Failure [failed lit_test] Build details are at https://buildbot.m-labs.hk/builders/artiq/builds/2979

13:35 <d_n|a> Also, it looks like the lit tests are somehow pulling in an old build of the compiler; that error is precisely what the PR fixes (tests pass locally)

13:44 <d_n|a> Reason tells me that it's probably a bug in the code, but I'm quite tempted to push those commits to master and take it from there...

13:59 <sb0> d_n|a: I don't know about set_log_level, but problems like the lit tests pulling an older version (and many other similar issues) is why we are using nix and hydra now

13:59 <sb0> it's not running lit yet, though (https://github.com/m-labs/nix-scripts/issues/3)

14:00 <sb0> d_n|a: did you run all the unit tests on your machine with the new firmware?

14:35 <bb-m-labs> build #2980 of artiq is complete: Failure [failed lit_test] Build details are at https://buildbot.m-labs.hk/builders/artiq/builds/2980 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>

15:05 <bb-m-labs> build #2500 of artiq-board is complete: Success [build successful] Build details are at https://buildbot.m-labs.hk/builders/artiq-board/builds/2500

15:07 <bb-m-labs> build #2981 of artiq is complete: Failure [failed set_log_level] Build details are at https://buildbot.m-labs.hk/builders/artiq/builds/2981 blamelist: Sebastien Bourdeauducq <sb@m-labs.hk>

15:11 <sb0> lit is running now

15:22 <sb0> also, the kasli responds correctly to the log_level command when I run it manually...

15:50 <bb-m-labs> build #2982 of artiq is complete: Failure [failed lit_test] Build details are at https://buildbot.m-labs.hk/builders/artiq/builds/2982 blamelist: David Nadlinger <code@klickverbot.at>

16:14 <d_n|a> (I've just double-checked to be sure, and the lit tests indeed pass locally on master. The error in 2982 is exactly what I get if I revert the compiler sources.)

16:15 <sb0> yeah it's just conda crap, the test passes on hydra

16:16 <sb0> https://nixbld.m-labs.hk/build/2222/log

18:10 <bb-m-labs> build #2501 of artiq-board is complete: Success [build successful] Build details are at https://buildbot.m-labs.hk/builders/artiq-board/builds/2501

18:14 <bb-m-labs> build #2983 of artiq is complete: Success [build successful] Build details are at https://buildbot.m-labs.hk/builders/artiq/builds/2983

21:05 <_whitenotifier-1> [nmigen] anuejn opened issue #53: Creating signals named like verilog keywords produces invalid verilog - https://git.io/fjkXQ

21:10 <_whitenotifier-1> [nmigen] anuejn opened issue #54: Hirarchy of submodules is not obvious from verilog - https://git.io/fjkXd

21:32 <_whitenotifier-1> [nmigen] programmerjake commented on issue #53: Creating signals named like verilog keywords produces invalid verilog - https://git.io/fjk1O

22:56 <_whitenotifier-1> [nmigen] whitequark commented on issue #53: Creating signals named like verilog keywords produces invalid verilog - https://git.io/fjkMs

23:05 <_whitenotifier-1> [nmigen] whitequark commented on issue #54: Hirarchy of submodules is not obvious from verilog - https://git.io/fjkMW