00:10 <_whitenotifier-1> [YoWASP/nextpnr] whitequark pushed 1 commit to develop [+0/-0/±1] https://git.io/JsJPA

00:10 <_whitenotifier-1> [YoWASP/nextpnr] whitequark ffc5bb2 - Update dependencies.

02:15 <Yehowshua> does nMigen support negedge?

02:17 <d1b2> <DX-MON> yes, when you define a ClockDomain(), one of the arguments the domain can take is clk_edge which defaults to "pos". This determines the domain edge sensitivity

16:44 <d1b2> <omkar45> can nmigen converted to verilog?

16:44 <d1b2> <zyp> yes

16:44 <d1b2> <omkar45> I was thinking to use liteDRAM to create a SDRAM core but the problem was my rest of the code for the system in verilog.

16:45 <d1b2> <omkar45> can you tell me how?

16:45 <d1b2> <zyp> although litedram is migen, not nmigen

16:46 <d1b2> <zyp> you probably want this: https://github.com/enjoy-digital/litedram/blob/master/litedram/gen.py

16:49 <d1b2> <omkar45> thanks

16:49 <d1b2> <omkar45> although there is one problem: Current version of the generator is limited to: - DDR3 on Lattice ECP5 FPGAs. - DDR2/DDR3 on Xilinx 7-Series FPGAs. - DDR4 on Xilinx Ultascale(+) FPGAs.

16:50 <d1b2> <omkar45> My device was iCE40HX4K and SDRAM of size 12MB

16:50 <d1b2> <omkar45> need to look into it more.

19:42 <d1b2> <twam> I want to do a relatively larger multiplication (~36 bits x 49 bits) on an ECP-5 which supports 36x36 in hardware. I don't need the result within a clock cycle. Is there an easy way so that nmigen/yosys can use in a sync'ed way?