00:59 <_whitenotifier-3> [nmigen-boards] hansfbaier synchronize pull request #152: add board support for QMTech XC7A35T core board and daughterboard - https://git.io/J3L4k

16:10 <lkcl> gatecat, cr1901_modern: wha-howwww :) just added dcache to libre-soc, which by not a small coincidence is entirely based on the microwatt one

16:11 <lkcl> compiled it for ECP5 with nextpnr, and it nearly took out my 64 GB RAM laptop

16:11 <lkcl> loadavg over 35, 34 GB RAM used up by yosys on the autoname phase

16:12 <lkcl> dang :)

16:27 <Yehowshua> whitequark, how does cxxrtl handle very wide additions? libgmp?

16:32 <whitequark[m]> nope, it does them chunkwise using c++ templates only

16:32 <whitequark[m]> no external libraries

16:36 <Yehowshua> sounds like you hand rolled bignum more or less

16:36 <Yehowshua> do you have a link to the templates?

16:36 <Yehowshua> Or I guess I'm asking you to dig up a link - if you're up to it

16:37 <whitequark[m]> https://github.com/YosysHQ/yosys/blob/master/backends/cxxrtl/cxxrtl.h

16:38 <Yehowshua> thx

21:23 <_whitenotifier-3> [nmigen-boards] hansfbaier synchronize pull request #152: add board support for QMTech XC7A35T core board and daughterboard - https://git.io/J3L4k

21:41 <_whitenotifier-3> [nmigen-boards] hansfbaier synchronize pull request #152: add board support for QMTech XC7A35T core board and daughterboard - https://git.io/J3L4k

21:43 <d1b2> <dub_dub_11> I have another question of the "I need a very specific verilog output syntax" variety, when I instantiate a PLL with python Instance("altera_pll", p_fractional_vco_multiplier = "false", p_reference_clock_frequency = "50.0 MHz", p_operation_mode = "direct", p_number_of_clocks = 1, p_output_clock_frequency0 = "36.000000 MHz", p_phase_shift0

21:43 <d1b2> = "0 ps", p_duty_cycle0 = 50, I get verilog altera_pll #( .duty_cycle0(32'd50), .fractional_vco_multiplier("false"), .number_of_clocks(32'd1), .operation_mode("direct"), which throws Error (14024): Parameter "duty_cycle" of instance "general[0].gpll" has illegal value "00000000000000000000000000110010" assigned to it. Possible parameter values are 1 to 99, inclusive. . Do I need to use a verilog wrapper, or is

21:43 <d1b2> there some syntax trick I am missing?

21:43 <d1b2> <dub_dub_11> now I think about it I can just not include the parameter and let it use the default and it will be fine

21:43 <d1b2> <dub_dub_11> still possibly a minor issue?

21:44 <d1b2> <zyp> try "50"?

21:45 <d1b2> <dub_dub_11> ...it was fine with that

21:45 <d1b2> <dub_dub_11> urgh

21:46 <d1b2> <dub_dub_11> the IP wizard uses ints

21:46 <d1b2> <dub_dub_11> but it also accepts strings?? and all the other parameters are strings of numbers... intel things

21:47 <d1b2> <dub_dub_11> but that did the job, ty