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<d1b2>
<mubes> Folks, is there something specific I need to do in order to use a registered I/O tx and rx on different edges on ECP5? I've configured by i/o with xdr=1 and that gives me an io pin with io.i, io.o, io.i_clk, io.o_clk and io.oe If, however, I assign io.i_clk.eq(k) and io.o_clk.eq(~k) then I get an error like telling me I've got conflicting clocks. In the real project the actual error is ERROR: IOLOGIC
<d1b2>
'pin_dbgif_0__tms_swdio.dbgif_0__tms_swdio_0$IOL' has conflicting clocks 'cmsisdap_dbgif_0__swdwr__o_clk' and 'cmsisdap_dbgif_0__tck_swclk__o' ...is it possible to run with differing clocks like this? Looking at the debug.v the ORF1P3DX and IFS1P3DX primitives have different clock signals, but something is getting tangled somewhere...
<whitequark[m]>
it might be a real P&R constraint
<whitequark[m]>
cc gatecat
<d1b2>
<mubes> the error is followed by the line ERROR: Packing design failed. so I'm guessing that's the step it falls over at.
<d1b2>
<mubes> I'm off to sleep on it. If anyone has any bright ideas I'm all ears.... g'night.
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<lkcl>
mubes: i am guessing here from the debug messages that you're attempting to develop a JTAG TAP interface?
<lkcl>
... dbgif ... >>>TMS<<< .... >>>TCK<<<<
<lkcl>
these are JTAG signals
<lkcl>
if that's the case, is there a reason why you would not wish to save a lot of time and use Chips4Makers C4M-JTAG?
<lkcl>
there could well be a good reason why you would want to reinvent that code, such as wishing to learn how to do posedge-negedge clocks and so on.
<lkcl>
ah neat - the *other* side of JTAG TAP. i always wanted to do that
<d1b2>
<zyp> and the reason it's bidirectional is because he's working on the swd interface, not the jtag
<lkcl>
ahh
<d1b2>
<mubes> In bed, but one last sneak at the phone :-)
<lkcl>
mubes: go sleep! :)
<d1b2>
<mubes> I can get up to 25MHz but 50MHz is my holy grail, and signal smearing means I need to sample on the proper edges at that speed.
<d1b2>
<mubes> I've tried using the DDR primitives, but they've got strange behaviour that I don't honestly understand, so I was trying to step back from those!
<lkcl>
well, C4M-JTAG may still help, it shows how to do posedge negedge on different clocks
<lkcl>
it's much more straightforward than you might imagine it to be
<d1b2>
<mubes> I'll take a look, could be really helpful, ta.
<d1b2>
<mubes> Yeah, these things generally are, once you know the tricks :-)
<whitequark[m]>
you almost certainly have to use IO blackboxes to actually get that to run at 50 MHz, not just posedge/negedge sampling in fabric
<lkcl>
just remember to sync the data using a FF chain (or use FFSynchroniser)
<lkcl>
whitequark[m]: ahh good point
<d1b2>
<zyp> that shouldn't be necessary with synchronous registered IO
* lkcl
currently running openocd at 5 khz to connect to 4 ECP5 GPIOs :)
<lkcl>
yes khz not mhz
<d1b2>
<mubes> Right, now I really am stepping away for a few hours. Night all.