00:30 <_whitenotifier-5> [YoWASP/nextpnr] whitequark pushed 1 commit to develop [+0/-0/±1] https://git.io/JOZZo

00:30 <_whitenotifier-5> [YoWASP/nextpnr] whitequark 33de3ed - Update dependencies.

15:34 <lkcl> quick report with source code links on doing JTAG testing at every level of the nmigen-based OpenPOWER SoC, Libre-SOC https://twitter.com/lkcl/status/1382718699497480193

15:35 <lkcl> i just managed today to get an FT232 to talk to c4m-jtag TAP interface that was on *actual* ECP5 GPIO pins

15:36 <lkcl> not the undocumented shift register "tap" inside the ECP5 https://github.com/emard/ulx3s-misc/blob/27338b0081b3b441f2fa77769350fa777bd3bcf9/examples/jtag_slave/hdl/top/top_jtagg_slave.v

22:30 <alanvgreen> the nmigen.hdl.Memory class has a simulate parameter in the constructor. What is the effect of setting simulate=True vs simulate=False ? The parameter isn't documented, so does that mean it can be ignored in most situations?

22:30 <whitequark[m]> it's a workaround for a deficiency for the current Python-based simulator implementation, which cannot deal with very large memories

22:31 <alanvgreen> I see. So can I mostly ignore it, or should I set simulate=False when generating rtl instead of simulations?

22:32 <whitequark[m]> you can ignore it

22:32 <whitequark[m]> it doesn't affect RTL output in any way

22:32 <alanvgreen> ty!