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<
_whitenotifier-5>
[nmigen-soc] Fatsie synchronize pull request #21: [WIP]wishbone.Connector class -
https://git.io/JJJhA
<
_whitenotifier-5>
[nmigen-soc] codecov[bot] edited a comment on pull request #21: [WIP]wishbone.Connector class -
https://git.io/JJJjf
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<
FL4SHK>
I'm abusing the `slice` type's `step` field
<
FL4SHK>
it's being used to represent "to" or "downto"
<
FL4SHK>
this is probably a bad idea
<
FL4SHK>
my_vector[0:2:"downto"]
<
FL4SHK>
my_vector(2 - 1 downto 0)
<
FL4SHK>
I have determined that the `slice.step` field isn't a good fit for VHDL
<
FL4SHK>
this is because ranges aren't necessarily constant like in Verilog/SV
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<
_whitenotifier-5>
[nmigen-soc] Fatsie opened pull request #28: CSR: Export Wishbone bridge from nmigen_soc.csr -
https://git.io/JOw8h
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_whitenotifier-5>
[nmigen-boards] hansfbaier synchronize pull request #142: Add board support for Terasic de0_nano -
https://git.io/Jtiqq
<
_whitenotifier-5>
[nmigen-boards] hansfbaier closed pull request #142: Add board support for Terasic de0_nano -
https://git.io/Jtiqq
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<
_whitenotifier-5>
[nmigen-boards] hansfbaier opened pull request #151: add board support for Terasic de0_nano -
https://git.io/JOrYO
<
_whitenotifier-5>
[nmigen-boards] hansfbaier commented on pull request #150: add DE0NanoPlatform -
https://git.io/JOrYz
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