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<lkcl>
dlb2: 4o: pin-pads have to be declared differently, you have standard IOpad cells with an "i/o/oe" triplet, and you also may have nets for enabling higher current and pullup/pulldown resistors (on each IOpad)
<lkcl>
you don't get a JTAG port, SRAM, PLL, or a DSP "for free", you have to do all those yourself
<lkcl>
and the tools have to be concerned about timing analysis, buffers, line-drivers / repeaters etc
<lkcl>
"<4o> @DX-MON @lethalbit what is the difference b/n your approach to asics and nmigen -> verilog -> yosys -> nextpnr -> whatever?"
<lkcl>
4o: so what did you mean?
<lkcl>
i assume you are asking "what is the difference between developing for an ASIC and developing for an FPGA which goes via nextpnr"?
<lkcl>
is that correct?
<lkcl>
happy to answer if you can clarify, because we're in the middle of doing the LibreSOC ls180 ASIC, with nmigen
<lkcl>
and started with an ECP5
<d1b2>
<4o> seems like i did. but i was wondering what are advantages:) and i'm responsible for several asics that's why i'm wondering if should take a closer look at proposed workflow
<lkcl>
oh you're asking what it's like for using *nmigen* for ASICs?
<lkcl>
(nextpnr5 is purely for FPGAs btw, hence the confusion / deducing you were asking about the difference between ASIC and FPGA development)
<d1b2>
<4o> > openlane support for nmigen using platform
<lkcl>
we're using coriolis2 not openlane
<lkcl>
it's under heeeavvy development
<lkcl>
tight deadline, apr 12
<d1b2>
<4o> that's a quote from yesterday by DX-MON
<lkcl>
basically once you have run "output to verilog please" from nmigen, it's .. err... well, exactly the same as if you'd written in verilog
<lkcl>
that's really all there is to it :)
<lethalbit>
Hi, sorry, I just checked IRC,
<lkcl>
details: nmigen output is, well, i can't say for sure if it's impossible to output unsynthesiseable designs, but it's a lot harder
<lkcl>
initialisation (reset values) are automatically inferred (as zero unless otherwise specified)
<lkcl>
you have to work quite hard to screw up, basically
<lethalbit>
So the way I implemented it is as an nmigen platform, so rather than generating the verilog and stuffing it into openlane this generates the openlane configuration based on the platform configuration and then invokes the tools automatically for you
<lethalbit>
so it would be something like
<lethalbit>
platform = sky130_fd_sc_hd()
<lethalbit>
then you pass your design to platform.build()
<lethalbit>
and *poof*
<lkcl>
lethalbit: whereabouts do you have a repo online?
<lethalbit>
it's a local fork atm
<d1b2>
<4o> so it's a fast-forward to openlate il?
<lethalbit>
because it's still janky
<lkcl>
in a few months time... that's ok, nobody cares: it still saves everyone else a hell of a lot of time
<lkcl>
in a few months time we'll be looking at an openlane build
<lethalbit>
yeah
<lkcl>
and it would be good not to have to duplicate that effort
<d1b2>
<4o> do you automate any part of openlane workflow as well?
<lethalbit>
once I get the ability to synth sync designs I'll think about a PR
<lethalbit>
because that's broken atm
<lkcl>
4o: the entire process in coriolis2 is automated.
<lethalbit>
4o, it does it all for you as long as you have openlane setup
<lkcl>
full build, P&R, IOpads placement, antenna, buffers, everything
<lethalbit>
uuuh, I can post a small example, one sec
<d1b2>
<4o> like python3 top.py generate -t gds:)
<lkcl>
lethalbit: that would be cool
<lkcl>
4o: not quite that automated, we run coriolis2 in a chroot :)
<lkcl>
makes it reproducible... at least that was the theory sigh (no git tags yet)
<d1b2>
<4o> ok, thanks. looking forward to pr
* lkcl
currently working with Chips4Makers to extract the post-P&R as VHDL and re-run the netlist under cocotb
<lkcl>
so after coriolis2 has done the P&R, there's a tool to extract the gate-level design (after repeater-buffers have been added etc.) as VHDL