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_whitenotifier-5>
[YoWASP/yosys] whitequark 110d68b - Update dependencies.
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FL4SHK>
seems that I want the `inspect` module
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FL4SHK>
I want to piggyback off of the VHDL implementation's error checking
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FL4SHK>
got told of the `inspect` module
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FL4SHK>
how does nMigen determine the line number of an Assert?
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FL4SHK>
I want to include Python line numbers of AST nodes in the generated VHDL
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FL4SHK>
only directly above every line in the generated VHDL
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FL4SHK>
so if someone could tell me how it's done in nMigen, that'd be great
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FL4SHK>
also, if this is too off topic for #nmigen, let me know
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FL4SHK>
what is `src_loc_at`?
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FL4SHK>
I see, so I'm not supposed to use that
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FL4SHK>
so I guess I can just use the `inspect` module
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cr1901_modern>
That was me being a bit flippant
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vup>
FL4SHK: basically how deep to look in the call stack for the location
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cr1901_modern>
You can use it, just be prepared for it to not work in a future python version
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FL4SHK>
I'll use stuff that'll work in future Python versions
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FL4SHK>
you can just use the `inspect` module
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vup>
can you get the location using `inspect`?
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vup>
ah yeah I see it
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FL4SHK>
figured it out!
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FL4SHK>
I think I need nMigen's tracer module
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FL4SHK>
though I had to do things differently for figuring out the line number
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FL4SHK>
actually, I just thought of another method
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FL4SHK>
The problem I had was having named AST elements know their name
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FL4SHK>
it'll get set by the DSL classes
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FL4SHK>
When an instance of one the DSL classes has its `__setattr__` function called, it'll create the AST node
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