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<kbeckmann>
alright, i will give it a shot.
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<sensille>
i guess it's time to look into pypy for simulation ...
<cesar[m]1>
kbeckmann: After manually reading the nmigen RTLIL and your verilog files on yosys, and running write_cxxrtl, I get myself a segmentation fault after the PROC_CLEAN pass.
<kbeckmann>
cesar[m]1: oh thanks for verifying. i didn't realize that i got a segfault, but yeah indeed i have a bunch of logs in coredumpctl.. but that's great, that should make debugging a bit easier.
<kbeckmann>
cesar[m]1: i figured out what was wrong by trial and error.. turns out that this type of code caused the crash "data_in_reg[addr[3 : 0]] <= write_data;". replacing it with a for-loop seems to work and i can now build a working simulation. it seems to work really well, cxxrtl is awesome.
<kbeckmann>
i'm not sure if that code is legal verilog or if it's a systemverilog thing, but the original code is synthesizable for ecp5 with yosys/nexpnr so that's why i was surprised that it didn't work "out of the box".
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<whitequark[m]>
that is a known yosys bug iirc
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<FL4SHK>
Decided to make my `PackedArray` class derive from `ValueCastable`
<FL4SHK>
though I'm indecisive
<FL4SHK>
What do I need the `like` staticmethod to do?
<FL4SHK>
guess I don't need the PackedArray
<FL4SHK>
I can just use `word_select()`
<FL4SHK>
though I think wimping out like I was thinking of doing isn't my best option
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<FL4SHK>
I think I'll just make it contain a Signal
<FL4SHK>
though if it's possible to have any `ValueCastable` within a `Record`, I think it makes more sense to bite the bullet and make it a `ValueCastable`
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<FL4SHK>
I want to be able to do a `PackedArray` of `Record`s
<FL4SHK>
as well as stick a `PackedArray` within a `Record`
<FL4SHK>
doing a `PackedArray` of `Record`s would mean I'd be able to do `packed_array[index].record_member`
<FL4SHK>
that's the behavior I'm after
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<vup>
FL4SHK: which `like` static method?
<vup>
you just need the as_value method, no?
<FL4SHK>
vup: within the `Record` and `Signal` classes
<FL4SHK>
I see
<vup>
I though you wanted to make it ValueCastable?
<vup>
like is just a method to get copy of the signal / record with the same shape
<FL4SHK>
ah, so I see that having a backing `Signal` is normal
<vup>
I don't know if it is normal :)
<FL4SHK>
well, it's at least something I can do
<vup>
I think this is the only place I have seen ValueCastable used apart from Record...
<vup>
but yeah, generally I think having a backing Signal is fine, after all, you need to lower your custom type to a signal at some point. The advantage of having ValueCastable instead of subclassing Signal is, that the custom data types don't have all the methods of Signal, for example for your datatype it might not make sense to have addition, but subclassing Signal means that will always be there...
<FL4SHK>
having `==` makes sense for my thing
<vup>
then you can implement it yourself...
<FL4SHK>
Yeah
<FL4SHK>
I was thinking of doing so
<FL4SHK>
I'll have `==` and `!=`
<FL4SHK>
though it may make sense to have `<`, `<=`, `>`, and `>=`
<FL4SHK>
seems like I won't be able to store a `PackedArray` within a `Record`
<FL4SHK>
due to `Record` not knowing about the `PackedArray`
<FL4SHK>
`PackedArray` is definitely not really a necessary class
<FL4SHK>
You can just use `word_select()`
<FL4SHK>
but I'll continue with it anyway
<vup>
yeah, I think a struct like thing instead of record is planned
<FL4SHK>
yeah, but does it include something like an array you can do `.eq()` with?
<vup>
no
<vup>
but you could put your Array into the Struct thing
<FL4SHK>
I'd really prefer that `Array` act more like a VHDL array
<FL4SHK>
you can assign to a whole array in VHDL and SV both
<FL4SHK>
and you can't in nMigen
<FL4SHK>
no `.eq()` exists for nMigen's `Array` class
<vup>
maybe, I did not really have a need for that yet
<FL4SHK>
I can give a real life example of it
<FL4SHK>
let's say you want to make an AXI4-Lite slave that has a register array as input and another register array for output
<FL4SHK>
I built one of these at work
<FL4SHK>
I had to encode the 2D arrays of bits I was using into 1D vectors
<FL4SHK>
because we were using VHDL 1993
<FL4SHK>
and not VHDL 2008
<vup>
I guess my main point of contention would be, what should happen if you don't put simple Signal's into the Array
<FL4SHK>
that's fair
<FL4SHK>
but maybe have a class that's an array of a single type?
<vup>
so having a special thing like PackedArray seems more suitable to me
<vup>
yeah
<FL4SHK>
I'd prefer to be able to have a `PackedArray` of `Record`s
<FL4SHK>
And I don't know how to do that
<FL4SHK>
a `Record` of `PackedArray`s would be nice as well
<FL4SHK>
or, well, a `Record` where an element is a `PackedArray`
<vup>
well Record currently looses all type information, so something like Struct (or the PackedStruct I linked above) would be needed for putting into Record
<FL4SHK>
I see
<vup>
but whats the problem with having a `PackedArray` of `Record`s?
<FL4SHK>
I suppose nothing
<FL4SHK>
I could just make `PackedArray` take an Element width and a size of the array
<FL4SHK>
then you could store it into a Record
<FL4SHK>
by just storing the width
<FL4SHK>
then you could decode the Record
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<FL4SHK>
I think nMigen would benefit from the ability to define a `:=` operator in Python
<FL4SHK>
but that `:=` operator isn't definable
<FL4SHK>
it's not a thing in Python
<sensille>
how can I check in elaborate if i'm in simulation?
<agg>
`platform is None`
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<FL4SHK>
can you do `Record.eq()`?
<FL4SHK>
in looking at the source code, it doesn't look like you can
<whitequark[m]>
no, on purpos
<whitequark[m]>
* no, on purpose
<FL4SHK>
I see
<FL4SHK>
That's something I'm used to being able to do
<whitequark[m]>
Record is still pending a redesign, which will happen but after some more important changes I'll announce soon
<FL4SHK>
I see
<Sarayan>
wq: new toys?
<whitequark[m]>
the project has a lot more social debt than it might seem at first
<whitequark[m]>
and i'll tackle that
<Sarayan>
what's social debt?
<whitequark[m]>
conceptually similar to technical debt
<whitequark[m]>
but more important for long-term existence and flourishing of the project
<Sarayan>
oh-kay?
<Sarayan>
not sure I'm getting the concept, but that's ok :-)
<Sarayan>
things need to be done, and you're doing them, so that's cool
<Sarayan>
KISS, where I'm the stupid :-)
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