#nmigen on 2021-04-16 — irc logs at freenode.irclog.whitequark.org

2021-02-27 05:40 whitequark[m] changed the topic of #nmigen to: nMigen hardware description language · code https://github.com/nmigen · logs https://freenode.irclog.whitequark.org/nmigen

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00:29 <_whitenotifier-5> [YoWASP/nextpnr] whitequark pushed 1 commit to develop [+0/-0/±1] https://git.io/JOCEg

00:29 <_whitenotifier-5> [YoWASP/nextpnr] whitequark 8c99768 - Update dependencies.

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05:56 <sensille> is the minerva risc-v core ready to use?

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07:06 <bsmt> i'm using it

07:08 <sensille> nice

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22:40 <FL4SHK> I am now working on my custom HDL thing

22:41 <FL4SHK> but it's going to just be a human-readable VHDL generator

22:41 <FL4SHK> with little to no error checking

22:41 <FL4SHK> and it'll enable me to use type generics and other cool things

22:41 <FL4SHK> I'm doing it in Python

22:51 <FL4SHK> how does nMigen get the name of a Signal besides the "name" argument?

22:51 <FL4SHK> oh wait

22:51 <FL4SHK> I have an idea

22:51 <FL4SHK> since entities and packages own named items

22:52 <FL4SHK> I can simply use setitem

22:52 <FL4SHK> `entity.my_signal`

22:52 <FL4SHK> and getitme

22:52 <FL4SHK> er, it was setattr and getattr

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