<cesar[m]1>
... that increments every clock cycle.
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<_whitenotifier-5>
[nmigen] cr1901 opened issue #604: In ECP5 and MachXO2 backends, is the `-forceAll` option necessary? - https://git.io/JYyUc
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<d1b2>
<twam> That's the hack I'm currently using but was hoping for something 'proper'. But then I'll stick with it for now.
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<agg>
cr1901_modern1: re your issue about the ecp5: i've noticed this too, it's really slow and does way more work than it seems like should be necessary, would be amazing to suddenly have all those builds be loads faster
<agg>
I hadn't looked in to why beyond a vague feeling that it was duplicating stuff from some output sections appearing multiple times, though
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<cr1901_modern1>
agg: I think the idea behaind -forceAll is to complement how the Diamond GUI does things (if an output artifact already exists, you can double click on it to rerun the build up to that point to refresh it)
<cr1901_modern1>
I don't think it's necessary for nmigen, but wq/others are free to override
<agg>
nmigen builds are all from scratch every time though, right?
<cr1901_modern1>
yes
<agg>
like, nothing should be being cached between runs anyway
<agg>
so what's the difference in having forceAll or not? in practice it seems like it causes a bunch of steps to get rerun?
<gatecat>
I think if you wanted to use -forceAll you would only call bitgen, not all the steps before it
<agg>
got it
<agg>
is it sort of doing an accidentally quadratic thing
<gatecat>
yeah exactly
<gatecat>
each step force-re-runs all the steps before it
<agg>
i just assumed the yosys+nextpnr chain was just that much faster :p
<agg>
probably not the only accidentally quadratic thing in all of diamond anyway
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<cr1901_modern1>
although Diamond complains if it doesn't have an empty work dir, I've never seen any indication that it changes the output
<cr1901_modern1>
(wrt to "nmigen builds are all from scratch every time")
<agg>
the script tells it to run each step so i assume all the outputs will be generated anyway, doesn't seem like it has a chance to reuse anything
<cr1901_modern1>
Yea that seems to be the case. You'll still get a warning tho, b/c why not?
<cr1901_modern1>
What Diamond actually meant was "my sel signal was completely optimized out"
<cr1901_modern1>
And I didn't notice until gatecat made the observation in the tweet
<agg>
you'd think it might manage to not warn about "no load" when in fact it optimised out the load
<cr1901_modern1>
When have the vendor tools ever done what we want them to do?
<agg>
once i finally found the right magic incantation i was quite pleased that bstool gives you a name for almost every config bit, that was helpful
<cr1901_modern1>
I haven't seen that yet, tbh. EPIC is nice tho. Would like nextpnr-machxo2 to have a GUI sooner or later, but it seems a bit off for now
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<sensille>
is the roundrobin scheduler from the lib ready to use? is there an example somewhere how to use it? i don't get the 'enableinserter' part
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<_whitenotifier-5>
[nmigen] whitequark commented on issue #604: In ECP5 and MachXO2 backends, is the `-forceAll` option necessary? - https://git.io/JYy7Z
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<sensille>
looks like my first module ported to nmigen takes up twice as many FFs. in the verilog version yosys inferred distributed RAM (DPR16X4) with 12 read ports for some registers. is the only way to get that back with by explicitely instantiating memory (with transparent read port)?
<d1b2>
<DX-MON> you should be able to use Memory primitive to get that
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<sensille>
x = Memory( ... )?
<sensille>
or is there also some other syntax?
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<d1b2>
<dub_dub_11> Yep Memory ()
<d1b2>
<4o> distributed ram could be generated from arrays
<sensille>
in verilog it did, but with the 1:1 translation to nmigen it somehow failed to do so
<d1b2>
<4o> failed in what way?
<sensille>
failed to recognize it as distributed RAM and fully expanded it to FFs
<d1b2>
<4o> ok, so all slices could act as ram in lattice devices. nice
<d1b2>
<4o> so ram could be mapped to block ram, luts and ffs on ecp devices. how Memory will know my intention?
<sensille>
i think block ram can't be transparent
<sensille>
i would think Memory() just passed that decision on to yosys
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<whitequark[m]>
block RAM can be transparent
<whitequark[m]>
yosys adds soft logic if necessary
<sensille>
on ecp5?
<sensille>
i probably misunderstood transparent :-/
<sensille>
what i meant is: block ram can't be async on ecp5
<whitequark[m]>
yes
<whitequark[m]>
or other FPGAs really
<whitequark[m]>
that i know of
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<agg>
4o: the synthesis tool guesses basic on the size of the memory and so forth whether to use FFs, dist ram, or block ram, or you can tell it specifically by using a ram_style attribute (block or distributed for example)
<agg>
sensille: what syntax are you using in nmigen to construct your 12-port memory? Array?
<sensille>
i used an array of signal(n). i wasn't aware that yosys implemented it as dist ram until i investigated where the diff in size comes from
<agg>
as in nmigen.Array?
<sensille>
on_ticks = Array([Signal(pwm_bits) for _ in range(npwm)])
<agg>
ah yea
<whitequark[m]>
arrays do not generally become memories
<whitequark[m]>
* arrays do not generally become block RAM
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<cr1901_modern>
whitequark[m]: Is the matrix acct your primary acct now? I need to privmsg
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