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<lkcl>
FL4SHK: i can confirm ghdl with yosys works well. i compile microwatt (--std=08) and also run cocotb tests extracting Alliance VHDL-formatted netlists pre- and post- layout/routing.
<Degi>
Just in case anybody wondered: On the ECP5-5G 381 package, pin PR38D can do 900+ MHz
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<lkcl>
Degi, wha-howw cool
<Degi>
Yes, its like 6x what the spec says
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<Degi>
Actually the limit wasn't the pin but the internal PLL
<Degi>
I might try using an SDR as a clock input (since I don't have any proper clock generators for that range)
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<Degi>
Oh, my SDR has a bit low output voltage
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<FL4SHK>
lkcl: that's good to hear
<FL4SHK>
whitequark[m]: so I've got a new problem that I think I've got some leads on due to thinking about how nMigen works
<FL4SHK>
the problem is that I need Python-side generics to be possible to cause creation of new entity, component, type, etc. declarations when you instantiate an object that is one of those things
<FL4SHK>
Up front I must say that I do not need an automated way for Python-side generics to get translated into VHDL-side generics
<FL4SHK>
so as far as the leads are concerned
<FL4SHK>
I believe I can just take inspiration from nMigen
<FL4SHK>
I can create `Elaboratable`
<FL4SHK>
I believe I'd have the `elaborate()` method return a VHDL AST node
<FL4SHK>
I don't know if that's all it'd take
<FL4SHK>
I'm a little lost
<FL4SHK>
please help me think of a solution if you can
<FL4SHK>
actually that is a request to anyone who can think of a solution to this
<FL4SHK>
might work to simply add AST nodes that specify to the AST lowering code that a new declaration is needed
<FL4SHK>
ooh, I just thought of this
<FL4SHK>
I can allow you to instantiate an entity declaration itself
<FL4SHK>
i.e. you can simply put the `Entity` AST node, which is the declaration of a VHDL `entity`, as your `Instance`'s entity type
<FL4SHK>
the language translator can decide where to put the declaration
<FL4SHK>
this works for types and components as well
<FL4SHK>
apologies for treating #nmigen as a rubber duck...
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<lkcl>
FL4SHK: lol
<lkcl>
if you can post the code location it's a lot easier btw
<lkcl>
less poultry involved :)
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<cr1901_modern>
lkcl: microwatt doesn't explode in RAM usage when trying to compile it w/ ghdl+yosys? Do you have a basic script I could test?
<lkcl>
cr1901_modern, you can use litex, it's about the easiest way to get up and running.
<lkcl>
from what i recall you have to make sure to pass --variant=standard+ghdl to the litex sim or versa_ecp5.py (or whatever FPGA) script
<cr1901_modern>
that's the issue... when I try to create a microwatt CPU w/ litex, the RAM usage explodes- yosys is using like 7GB for a renaming pass
<cr1901_modern>
and I eventually have to ^C the bui;d
<lkcl>
ah right. i have a 64 GB RAM laptop, my brother got me, last year.
<lkcl>
microwatt and libre-soc are not small, it's just down to OpenPOWER being really very sophisticated and suited to high-end
<lkcl>
both of them compile to around 20k LUT4s on an ECP5
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<gatecat>
a workaround is probably to patch autoname out of synth_ecp5
<gatecat>
and longer term fix it to be less memory intensive on complex cases like this
<gatecat>
there's no reason it should take 7+GB of RAM to build otherwise, Rocket is considerably larger and iirc Yosys peaks at <2GB (and nextpnr considerably less than that)
<cr1901_modern>
gatecat: Rocket is Chisel, correct?
<gatecat>
yeah
<gatecat>
I'm not counting Chisel memory usage though
<gatecat>
only from Verilog onwards, using the LiteX flow
<cr1901_modern>
ahhh
<cr1901_modern>
Part of the reason I've been dragging my feet about reporting this is because Idk if it's a yosys problem, or a ghdl problem. The plugin AIUI converts to RTLIL
<cr1901_modern>
Or rather, at the very lease, doesn't convert VHDL to Verilog
<gatecat>
cr1901_modern: I've seen bad autoname performance on other cases too, it's definitely just autoname failing to work well in some cases (very long paths iirc)
<cr1901_modern>
Is autoname required to get synthesizable output json? If not, would you accept a patch to selectively disable it (via an option) if I can show a benefit for microwatt (not sure when I'll get to this- prob this weekend)?
<cr1901_modern>
Right now on my 8GB Linux machine, the microwatt cache number of words has to be reduced by a large amount so that autoname doesn't explode
<gatecat>
no, it's not required at all
<gatecat>
ny hack for the snes core was to just run to :check and then call write_json manually