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<povik>
hi all
<agg>
o/
<povik>
there's one aspect of migen's clock domains i am not clear on. do clock domains with identical names get merged across modules?
<povik>
i.e. are they the same clock domain?
<agg>
yes, unless created with local=True in which case they only merge down the hierarchy
<agg>
(well, 'merged' maybe isn't the right word, they only exist once, it would be an error to create a new domain with the same name, but you can assign to them based on name anywhere down the hierarchy)
<povik>
so unless created with local=True, the clock domain is created once and then available in any module implicitly?
<agg>
yes
<povik>
i see. thanks
<agg>
and you can refer to it by the name as a string using m.d[name], for instance to pass a string domain name into a submodule as an argument
<agg>
or the normal m.d.name if the name is 'fixed'
<povik>
what does that mean? does that relate to clock domain renaming?
<agg>
usually though, the preference is to always use sync in a module, and use DomainRenamer when you instantiate the module to move it into whichever clock domain you want
<agg>
typically a module only cares about clock domains besides comb and sync if it's either your top-level module or is doing some clock-domain crossing
<agg>
so usually you'd just use sync in the module implementation, and use DomainRenamer with the name of the new domain when you instantiate it, but if you are doing CDC inside the module, usually you'd pass a domain name string in and the module would use m.d[name] to put statements in the right domain
<agg>
it's valid to just create pixclk in top and then use m.d.pixclk elsewhere, it works, but it makes the code a bit less modular, depends on your preference i guess
<agg>
for example if you look at SyncFIFO in the nmigen lib, it's always in "sync", but you could use DomainRenamer to put it somewhere else; however PulseSynchronizer has an i_domain and o_domain argument, so you can tell it which domains you're synchronizing between
<povik>
ah, i didn't know what you meant by name being 'fixed', but now I see, it's just a matter of knowing what the name is going to be at coding-time
<povik>
now it seems all clear
<povik>
i suppose DomainRenamer is recursive and applies to submodules as well?
<Sarayan>
yes, it does
<povik>
great
<Sarayan>
also, don't neglet demainrenaming clock+enable combos, that can be really nice
<agg>
right, if you know the name when you're writing the code you can access it as an attribute of m.d, otherwise if it's inside a variable you can use the dictionary lookup instead (same thing under the hood anyway)
<Sarayan>
agg: I think you can domainrename to a known fixed internal name from a parameter to avoid passing name around and/or making things in general a little more readable
<agg>
that's how a lot of things worked in migen but I think having domain arguments for CDC things is a lot more convenient (and incidentally more performant?)
<agg>
so definitely "just use sync in generic modules, then rename later"
<agg>
but for something doing CDC, passing in the domain names is way neater than domainrenamer with a dict of clock domains to remap which needs to be used every single time you use the cdc module?
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<povik>
Sarayan: clock+enable combos? looking at DomainRenamer it appears to rename clocks and resets only
<Sarayan>
m = EnableInserter({"pclk": self.i_pclk, "nclk": self.i_nclk})(m)
<Sarayan>
m = DomainRenamer({"pclk": "sync", "nclk": "sync"})(m)
<Sarayan>
and then you use m.d.pclk/m.d.nclk everywhere
<Sarayan>
agg: I'm ok with passing domain names, I'm saying the CDC-doing-module can internally domain-rename
<Sarayan>
so that the external code is simple and the cdc code is simple too, the renaming in the cdc code doing the glue
<povik>
must look up EnableInserter
<agg>
Sarayan: oh, sure, agreed
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<povik>
Sarayan: that indeed seems nice
<povik>
well, thank you for the office hours, see you around
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* lkcl
agrees with agg, definitely don't try to rename domains throughout your code.
<lkcl>
ah he's gone from the channel. maybe see that from irclogs later
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<Degi>
How can a generic FT232H (or similar) chip be used as a JTAG interface for FPGAs? Does it just work out of the box with OpenOCD or do I need to configure it somehow?
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