01:46 <mithro> [OffTopic] I thought some people in this channel might like https://dberard.com/home-built-stm/

04:00 <_whitenotifier-5> [nmigen] github-4o opened issue #608: [RFC] get rid of that `+=` and `.eq()` - https://git.io/JOT9i

04:07 <_whitenotifier-5> [nmigen] github-4o edited issue #608: [RFC] get rid of that `+=` and `.eq()` - https://git.io/JOT9i

06:09 <_whitenotifier-5> [nmigen] whitequark commented on issue #608: [RFC] get rid of that `+=` and `.eq()` - https://git.io/JOkJa

06:10 <_whitenotifier-5> [nmigen] whitequark edited a comment on issue #608: [RFC] get rid of that `+=` and `.eq()` - https://git.io/JOkJa

08:58 <sensille> is there a helper to determine the number of bits needed to represent a range, like it would be automatically done with Signal(range())?

12:47 <_whitenotifier-5> [nmigen-boards] Freax13 opened pull request #150: add DE0NanoPlatform - https://git.io/JOk7Q

15:29 <tpw_rules> sensille: for range(x) there is (x-1).bit_length() which is a python thing

15:30 <sensille> nice, thanks

16:43 <_whitenotifier-5> [nmigen-boards] Freax13 synchronize pull request #150: add DE0NanoPlatform - https://git.io/JOk7Q

16:59 <d1b2> <4o> cool, de0nano comming to nmigen

18:42 <d1b2> <dub_dub_11> I tried to synth something for ECP5 and got an error from yosys ERROR: Module `\SGSR' referenced in module `\cd_sync' in cell `\U$$3' is not part of the design. . I saw the previous issue with support for this primitive, so I'm assuming I have set up the toolchain wrong somehow.

23:44 <mwk> do you have a git version of yosys from after Aug 2019?

23:59 <d1b2> <dub_dub_11> should do