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<whitequark>
I don't anticipate Values to gain any knowledge of the object from which they've been cast; that would change the current approach to compilation (lowering) into a completely different one, with end-to-end correspondence of effectively two PLs embedded in a third
<whitequark>
however, there might be another way to do what you want
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<lkcl>
whitequark: you saw the segfault in write_cxxsim "goes away" if a yosys "memory" pass is added?
<whitequark[m]>
sure
<whitequark[m]>
if you have a minimal test case, i'll be happy to fix the underlying bug
<lkcl>
1 sec let me track it on irc log from yesterda
<lkcl>
that was easy. ahh and the "memory" pass i am guessing would have done that
<whitequark[m]>
even just doing proc before flatten would do it
<whitequark[m]>
it's a subtle pass sequencing issue
<whitequark[m]>
well, the segfault was caused by a subtle pass sequencing issue. the bug was there regardless
<lkcl>
the slightly scary bit now is that we have to do *gate-level* cxxsim
<lkcl>
using the VHDL cell library definitions, and the VHDL-subset-output from coriolis2
<lkcl>
is it possible to do individual modules with write_cxxsim?
<whitequark[m]>
what do you mean?
<lkcl>
coriolis2, after it's done its layout, can extract the entire netlist *back* out as subset VHDL files (!)
<lkcl>
we want to simulate that using cxxsim
<lkcl>
but, to give some idea of the size: compiling those (350) files with ghdl resulted in a whopping 160 mb simulation binary
<lkcl>
if i try to do write_cxxsim on the entire design it's quite likely to result in a cpp file of several hundred thousand lines in length
<whitequark[m]>
that's normal
<lkcl>
(because it's gate-level)
<lkcl>
compilation time could be several hours
<whitequark[m]>
several million is more likely
<whitequark[m]>
yes
<lkcl>
yeah
<whitequark[m]>
that's expected with gate level cxxrtl models
<lkcl>
i'd like to be able to do that as a parallel build
<lkcl>
by having multiple separate cpp files, one per module
<whitequark[m]>
are you not flattening?
<lkcl>
at the moment (before P&R) i'm just doing "write_cxxsim"
<whitequark[m]>
that flattens everything into a single module
<lkcl>
i'm wondering / exploring what the possibilities here
<lkcl>
yes. which is fine for the pre- P&R one
<whitequark[m]>
if you don't flatten, you get a severe performance penalty
<lkcl>
takes 12 minutes, the output (ls180.cpp) is 60,000
<lkcl>
okaaay
<whitequark[m]>
try running your design with `write_cxxsim -noflatten`
<whitequark[m]>
and check the return value of `p_top->eval()`
<whitequark[m]>
not flattening slows down your simulation by a factor of at least that much, in reality probably an order of magnitude more
<lkcl>
well, that might be ok. we'll only be running for a few thousand clock cycles
<whitequark[m]>
this is still the case for non-flattened gate-level simulations
<lkcl>
i can live with that: the program being "run" is only 6 instructions long
<whitequark[m]>
it is likely that the gain from parallel compilation will be more than offset by the performance hit of `-noflatten`
<whitequark[m]>
I recommend running a compilation (for several hours, yes) with `write_cxxrtl -noflatten` on the gate level netlist first, and considering whether the reduction in performance is worth the potential gain from parallelized build
* lkcl
thinks
<lkcl>
ok i'll experiment
<lkcl>
but it's at least possible?
<whitequark[m]>
no, because according to my measurements, it provides no benefit
<whitequark[m]>
(that is, there is no option to use a file per module)
<lkcl>
ahh
<whitequark[m]>
i was never able to find any significant end-to-end performance improvement, no matter the scenario, from simulating non-flattened netlists
<lkcl>
interesting
<whitequark[m]>
and if you have a flattened netlist, it is just one module anyway
<whitequark[m]>
it would be, essntially, trivial to add an option to split everything with a module per file
<whitequark[m]>
i just don't see any point in it
<lkcl>
ahh i remember an option that verilator has. the (flattened) netlist is still split out into multiple cpp files
<lkcl>
that gives the best of both worlds
<whitequark[m]>
verilator does things very differently
<whitequark[m]>
that doesn't necessarily mean better. in some scenarios, cxxrtl is already faster than verilator
<lkcl>
cool :)
<whitequark[m]>
it would not be easily possible to adapt what verilator does to cxxrtl. in general, i consider cxxrtl a simulator in a class of its own, rather than "verilator for yosys"
<lkcl>
yeyeh
<lkcl>
i really must try not to get distracted by wishing to see these things for myself, you know what i mean :)
<lkcl>
and trust the research you've done
<whitequark[m]>
you can do what i suggested and evaluate whether there is a performance benefit
<whitequark[m]>
if there is, i'll happily update cxxrtl to have the option you want
<lkcl>
appreciated
<lkcl>
it's an intriguing counter-intuitive thing
<whitequark[m]>
the implementation can get rather annoying, e.g. people will also want build system integration that is required for compiling multiple files, and such
<whitequark[m]>
the current implementation is much easier to integrate, since it is just two fixed files
<whitequark[m]>
(one in some cases)
<lkcl>
yeyeh
<kbeckmann>
neat, fyi the above PR also solves the problem i had a few days ago with the same root issue (array access with a wire as an index).
<lkcl>
anyway - thank you for this amazing work.
<lkcl>
kbeckmann: cool.
<whitequark[m]>
kbeckmann: glad to hear it!
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<jfng>
... I hit this exact bug yesterday (by simulating litedram with cxxrtl), and this PR fixed it
<jfng>
thank you !
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<Funca>
Hi! I've got a question regarding verification.
<Funca>
When I try to verify a module I can see that the engine injects data through the ports, but I was wondering if it could also do it in uninitialized registers?
<Funca>
I've tried it with reset_less=True but it doesn't work
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<FL4SHK>
whitequark: I see
<FL4SHK>
I'll have to think about how to do this once I set up my own HDL
<FL4SHK>
I'm currently making a statically typed interpreted language intended for making DSLs
<FL4SHK>
I plan on stealing some ideas from nMigen for it
<FL4SHK>
using multiple HDLs is fun
<FL4SHK>
not so much for the same project
<FL4SHK>
but for multiple projects? Yes please
<FL4SHK>
I also want to borrow ideas from VHDL and SV
<FL4SHK>
spitting out human-readable Verilog and VHDL would be the goal
<FL4SHK>
maybe just VHDL
<whitequark[m]>
ambitious
<FL4SHK>
since apparently you can do formal verification with GHDL synthesis
<FL4SHK>
yes
<FL4SHK>
I've started writing up the interpreted language's grammar
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