whitequark[m] changed the topic of #nmigen to: nMigen hardware description language · code https://github.com/nmigen · logs https://freenode.irclog.whitequark.org/nmigen
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<FL4SHK> Hello world
<FL4SHK> I have come back to nMigen
<FL4SHK> I want to create a class representing a packed array
<FL4SHK> I've started work on it
<FL4SHK> and, IIRC, I want to use ValueCastable as the base class
<FL4SHK> I have no idea how to use ValueCastable
<FL4SHK> I *was* going to just use `Signal` as the base class
<FL4SHK> but I feel like that's not the intended way
<FL4SHK> I'll just leave it as derived from `Signal` for now
<FL4SHK> this isn't very complex
<FL4SHK> just a small wrapper thing
<Sarayan> just for my curiosity, why do you need that wrapper?
<Sarayan> what's the use case?
<FL4SHK> Sarayan: it allows me to avoid typing the `.word_select()` and use more natural `[]`
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<FL4SHK> I believe it flat out needs to derive from `Signal` due to that
<Sarayan> ah, makes sense
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<FL4SHK> Sarayan: oh yeah, another thing I thought of while I was AFK
<FL4SHK> this thing works with arrays of Record
<FL4SHK> well, they get implemented such that you could put it on a "port"
<FL4SHK> I always put module ports into a class
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<FL4SHK> seems my PackedArray class isn't working
<FL4SHK> fixed
<FL4SHK> seems you can't assign to an `Array`
<FL4SHK> good thing I made this `PackedArray` class
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<_whitenotifier-5> [nmigen] jfng opened issue #605: Nesting Parts with a variable offset throws an AssertionError - https://git.io/JYd5G
<d1b2> <4o> is there an option to ask nmigen ask yosys to run opt before dumping vlog
<d1b2> <4o> ?
<d1b2> <4o> yep, definitely want to opt generated vlog: that fixes simulation with icarus. can i do it with nmigen or the only way to do it is dump il and convert it to vlog with a custom yosys script?
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<agg> it's not directly exposed but it looks like you can add custom yosys commands
<agg> oh, no, I take it back, it's not there.
<agg> probably easiest thing for right now is to copy nmigen.verilog._convert_rtlil_text into your own code and add opt to the script it writes
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<kbeckmann> whitequark[m]: i did some slight changes to _convert_rtlil_text to accept black boxes written in verilog and tried it out together with nMigen code. works great for a blinky. however when i try it with a more complex design, it fails and I don't understand why. yosys exits with an error code (-11) and I am not sure how to debug further. running yosys with -v 100 gives some prints but not really any
<kbeckmann> hints to what may be wrong.
<kbeckmann> so my question is if you have any hints on how i should go about debugging this. are there some flags i should pass yosys or add to the script that might be helpful?
<kbeckmann> i'm not sure if it's a bug in yosys of if i'm just doing something wrong so i haven't opened an issue about this. the test project can be found here if curious https://gist.github.com/kbeckmann/2980e9f7371e3ce8cc79a415e0a4248b
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<whitequark> kbeckmann: i do not have time to look into it at the moment; you're on your own