<agg>
you should `app_addr = yield self.app_addr[1:3]`
<agg>
after you've yielded, app_addr is just an integer, not a signal
<agg>
you could use (yield self.app_addr[1:3]) there
<agg>
slan: ^
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<slan>
Well that's the thing... either I yeild and get an integer that works in word_select, or I use self.app_addr[1:3] (a signal) but then it doesn't work
<slan>
No it does not (and it shouldn't IMO) : TypeError: Received unsupported command ((slice (sig app_addr) 1:3), 32)
<agg>
I think the brackets might be mismatched
<agg>
it looks like it's yielding (self.app_addr[1:3], 32) but should just be (self.app_addr[1:3])
<agg>
(the line I posted has correct brackets I think)
<agg>
why don't you think it should work?
<GenTooMan>
hmm I found out how to get version information from nmigen about it's version and the yosys it's using.
<slan>
I was assuming the whole expression had to be in the "non-python" real (if that maskes sense). Now I see I probably had some fundamental misunderstanding... this works as expected.
<slan>
Now time to figure out why :) esp. why not mem_rp.data.word_select(self_app_addr[1:3]), 32) directly as I would write in non-simulation code...
<slan>
Thanks agg!
<slan>
(reason for the "non-python" idea is I do a signal.eq(...) in the first place...
<agg>
No problem, glad it worked :) the latter doesn't work because word_select in simulation needs a constant and you're giving it a signal, it doesn't know how to request it from the simulator
<slan>
Yeah, makes sense
<slan>
also note I have liberally put some yield Settle() here and there, guessing I need to give the sim some breathing room to propage my almost-entirely combinatorial design
<slan>
thos have been put there mostly by trial-and-error, but as a rule of thumb, anything you signal.eq(...) and expect to get some result needs a Settle(). Am I on the right mindset?
<agg>
Someone better informed as to the workings of the simulator could give a better answer but yes, that's my understanding, you can yield Settle to trigger an update of all the combinatorial logic after you update some inputs
<slan>
Cool! I'm having a blast exploring nmigen (and hardware design), props to @whitequark and the community to lower the barrier and make it available to software devs
<agg>
(for synchronous logic testing I basically never use settle and instead I'm setting inputs to take effect next cycle, so just use plain yield, but for combinatorial logic testing you need settle)
<slan>
I see. For my experiments, I'm actually trying to do as much in combinatorial as possible. Feels like I can always draw some line later on with clocks. Doing it the other way around seemed a bit more tricky (for me).
<slan>
(as in: I don't think I have a good intuition on where to impose a clock cycle, so by letting evrything go combinatorial and ask my impl tool to show me the critical path I am better informed on how to partition my design)
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