whitequark[m] changed the topic of #nmigen to: nMigen hardware description language · code https://github.com/nmigen · logs https://freenode.irclog.whitequark.org/nmigen
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<_whitenotifier-5> [YoWASP/nextpnr] whitequark pushed 1 commit to develop [+0/-0/±1] https://git.io/JYEzN
<_whitenotifier-5> [YoWASP/nextpnr] whitequark 5066742 - Update dependencies.
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<_whitenotifier-5> [YoWASP/yosys] whitequark pushed 1 commit to develop [+0/-0/±1] https://git.io/JYEV7
<_whitenotifier-5> [YoWASP/yosys] whitequark 5ea888f - Update dependencies.
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<_whitenotifier-5> [nmigen] github-4o opened issue #603: yosys error on particular nmigen code - https://git.io/JYE9N
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<key2> anuejn: it's interesting you are building a class-d amp ?
<key2> anuejn: I though a while ago converting this one to nmigen: https://github.com/YetAnotherElectronicsChannel/FPGA-Class-D-Amplifier
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<anuejn> key2: i did read that one and definitely took inspiration from it ;)
<anuejn> (more the docs than the actual code tho)
<anuejn> also i opted for some more abstractions (e.g. a fixed point library)
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<GenTooMan> key2, should it not say PDM? (Pulse Domain Modulation) PWM has a fixed frequency and the width of the pulse is varied based on N. PDM is not fixed frequency and modulates the output based on the input frequency and distributes the transition average based on N. In other words the average number of 1's and 0's in the stream is the number, not the period of a 1 or 0 contiguous stream. This is own delta sigma modulation works
<GenTooMan> (last this poor soul checked anyhow).
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<GenTooMan> (sigh) own == how, don't ask why I used the word own because I don't even know.
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<vup> GenTooMan: i think its a multi bit sigma-delta modulator feeding into PWM, so the output is actually PWM
<DX-MON> aaa, the wife's gone and done an awesome and I'm trying to encourage her (lethalbit) to PR it.. OpenLANE support for nMigen using platforms
<Sarayan> tbh I'm intrigued by the twitter handle ;-)
<agg> ooh, cool
<agg> if nothing else it would be really fun to see what some designs would hypothetically look like in silicon :p
<agg> has she tried it with something bigger like a risc-v core?
<DX-MON> now to convince her to commit the changes and PR them XD
<DX-MON> not.. yet.. but I think that's something she wants to try
<DX-MON> (lethalbit is welcome to pipe up right about now)
<agg> once an inverter works, why not go big, right
<lethalbit> I'm working on it,
<lethalbit> it's kinda fiddly to get the process settings to behave
<lethalbit> but eventually I wanna try the minerva core once I think it's "good enough"
<agg> i have no idea about asic stuff at all, does it take ages to, uh, synthesis (?) compared to fpga designs?
<agg> synthesise* i guess
<lethalbit> honestly, nor do I, lol
<lethalbit> but yeah, the whole process takes a while and generates lots of very large files
<lethalbit> currently the flow only works with comb logic
<lethalbit> there is still issues with clocked designes
<lethalbit> mainly the whole domain synth
<lethalbit> *shrug*
<lethalbit> I was just playing with the idea anyway, not like it's PR worthy
<d1b2> <dub_dub_11> looks awesome 🙂
<sensille> i guess this is more of a generic python question, but i can't really find an answer ... sim.add_sync_process complains about my function not being a generator function. how does python determine that?
<agg> sensille: it needs to have a 'yield' statement in it somewhere
<DX-MON> by the presence of yield statements
<agg> and also (in this particular case) it shouldn't take any arguments and shouldn't yet have been called, so you'll often see a pattern like: def make_tb(arg): def tb(): yield x.eq(arg); return tb
<sensille> agg: it does
<sensille> it has an argument, though
<DX-MON> are the yield statements directly in the body of the function, or inside a function it defines?
<agg> have you already supplied the argument, too?
<agg> you need to pass the function object to add_sync_process, not the result of calling the function
<sensille> m(
<sensille> thanks :)
<agg> (so if it takes an argument, and you've called it with that argument, you're passing its return value to add_sync_process)
<sensille> yeah, so obvious :-/
<agg> not sure about "obvious" :p
<agg> at least it's not also using async, I guess
<agg> (I really like the generator interface to the simulator, to be clear)
<sensille> so can i get arguments directly into the function, or just via a closure?
<sensille> doesn't seem so
<DX-MON> you can.. by making a function that returns a generator
<agg> the generator you pass to add_process can't have been started yet, so there's no way to give it arguments, a closure is the way to go
<sensille> great, that wasn't too hard :)
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<GenTooMan> vup, hmm well I was wondering what the consequence with the low pass filter that would have mostly. The order of the filter would have to increase I suspect, but I haven't tested that theory so it's mere speculation. Still it's a pretty cool tool to use. Delta sigma are excellent for isolation.
<vup> Yeah, I have been wondering about that aswell, someday I will have the time to do some investigation :)
<GenTooMan> vup, well I have wandered back into audio design world. So for me it's sooner than later.
<vup> well, if you do some formal investigation sometime, feel free to ping me with your results :)
<GenTooMan> vup, hmm I'll let you know if I don't get a boot to the head type of interruption.
<vup> :)
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<anuejn> hm... somehow I missed some kontext to understand your dialogue
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