00:29 <_whitenotifier-5> [YoWASP/nextpnr] whitequark pushed 1 commit to develop [+0/-0/±2] https://git.io/JYO0D

00:29 <_whitenotifier-5> [YoWASP/nextpnr] whitequark 42d012c - Update dependencies.

09:01 <fdsa> Hey team, I love nmigen so far, but I'm having trouble finding information on how to combine nmigen files with legacy verilog code. Is it possible to write something in verilog (a dq ff for example), and access the ports in nmigen?

09:09 <jeanthom> fdsa, yup it's possible! You have to create an Instance for your verilog entity: https://git.sr.ht/~macbook/kilogueur/tree/master/item/soc/usbcore_wrapper.py#L25-37 and then import the verilog file into the platform: https://git.sr.ht/~macbook/kilogueur/tree/master/item/soc/ecpix5.py#L125-126

09:27 <fdsa> amazing thank you!

09:58 <fdsa> one more question, I'd like to simulate the things in the .v file, and it seems that the only way to do this is to use the 'cxxrtl backend', but how is this done? any other ideas? thanks

10:01 <jeanthom> I haven't touched CXXRTL in ages so I can't really help you, but there's this article: https://tomverbeure.github.io/2020/08/08/CXXRTL-the-New-Yosys-Simulation-Backend.html

10:01 <jeanthom> Otherwise you can export your whole design to Verilog and simulate it with your favorite verilog simulator

10:03 <fdsa> ah thanks

10:03 <jeanthom> ooh seems like cxxsim is now integrated in nMigen: https://github.com/nmigen/nmigen/issues/564

10:04 <fdsa> interesting!

10:10 <jeanthom> I'm not sure you can use it for mixed-languages simulations though, as you're feeding your verilog file to platform

10:11 <jeanthom> and if I remember well nMigen's simulator doesn't use platforms at all

10:24 <whitequark[m]> not yet

15:25 <_whitenotifier-5> [nmigen-boards] twam opened pull request #149: Add RGMIIResource - https://git.io/JYsPf

20:26 <kbeckmann> is there a neat way to rotate_left signals that are little endian? i've run in to a snag where i have to rotate a 32 bit little endian word by 12 positions which ends up garbled. just asking in case anyone has done this before and i don't have to reinvent the wheel :)

20:53 <kbeckmann> nevermind.. i had mixed endianess in my code which was just a bad thing to do.. keeping things consistent makes life easier.