whitequark[m] changed the topic of #nmigen to: nMigen hardware description language · code https://github.com/nmigen · logs https://freenode.irclog.whitequark.org/nmigen
<_whitenotifier-5> [YoWASP/nextpnr] whitequark pushed 1 commit to develop [+0/-0/±1] https://git.io/JqviQ
<_whitenotifier-5> [YoWASP/nextpnr] whitequark 1f6530e - Update dependencies.
oter has quit [Quit: Textual IRC Client: www.textualapp.com]
lf has quit [Ping timeout: 240 seconds]
lf has joined #nmigen
richbridger has quit [Remote host closed the connection]
richbridger has joined #nmigen
revolve_ has quit [Read error: Connection reset by peer]
Stary has quit [Ping timeout: 260 seconds]
revolve has joined #nmigen
Stary has joined #nmigen
Degi has quit [Ping timeout: 240 seconds]
Degi has joined #nmigen
PyroPeter_ has joined #nmigen
PyroPeter has quit [Ping timeout: 245 seconds]
PyroPeter_ is now known as PyroPeter
Bertl_oO is now known as Bertl_zZ
bvernoux has quit [Quit: Leaving]
peepsalot has quit [Quit: Connection reset by peep]
peepsalot has joined #nmigen
emeb_mac has quit [Quit: Leaving.]
jeanthom has joined #nmigen
cr1901_modern has quit [Ping timeout: 260 seconds]
chipmuenk has joined #nmigen
levi_ has joined #nmigen
bubble_buster_ has joined #nmigen
sorear_ has joined #nmigen
mithro_ has joined #nmigen
XgFgX has joined #nmigen
XgF has quit [Disconnected by services]
miek___ has joined #nmigen
sorear has quit [*.net *.split]
levi has quit [*.net *.split]
miek has quit [*.net *.split]
mithro has quit [*.net *.split]
bubble_buster has quit [*.net *.split]
bubble_buster_ is now known as bubble_buster
levi_ is now known as levi
sorear_ is now known as sorear
mithro_ is now known as mithro
revolve has quit [Read error: Connection reset by peer]
revolve has joined #nmigen
miek___ is now known as miek
XgFgX is now known as XgF
jeanthom has quit [Ping timeout: 246 seconds]
richbridger has quit [Ping timeout: 256 seconds]
cr1901_modern has joined #nmigen
jeanthom has joined #nmigen
jjeanthom has joined #nmigen
jeanthom has quit [Ping timeout: 260 seconds]
revolve has quit [Read error: Connection reset by peer]
revolve has joined #nmigen
jjeanthom has quit [Ping timeout: 260 seconds]
Bertl_zZ is now known as Bertl
jjeanthom has joined #nmigen
jeanthom has joined #nmigen
jjeanthom has quit [Ping timeout: 260 seconds]
jeanthom has quit [Remote host closed the connection]
jeanthom has joined #nmigen
emeb_mac has joined #nmigen
jeanthom has quit [Ping timeout: 265 seconds]
jeanthom has joined #nmigen
peeps[zen] has joined #nmigen
peepsalot has quit [Ping timeout: 260 seconds]
revolve has quit [Read error: Connection reset by peer]
revolve has joined #nmigen
hexastorm has joined #nmigen
jjeanthom has joined #nmigen
<hexastorm> I am trying to implement de casteljau algorithm for moving motors along bezier curves with a FPGA..
jeanthom has quit [Read error: Connection reset by peer]
<hexastorm> for it I need multiplication, do I need to enable multiplication in yosys?
<hexastorm> or does yosys just fix it somehow? how many multiplication operators can I use?
<agg> what FPGA? ideally yosys would infer the use of a hardware multiplier, if your FPGA has them, but you can check if it has done so in the resource usage report from yosys or from nextpnr
<hexastorm> does yosys simplify 2a to a+a (and not carry out multiplication) and does it fix a*b with a*b in real multiplication
<hexastorm> I have ice40hx4k ( I don't think it has a dsp)
<agg> yea, it doesn't have any multipliers, so it would all be in logic
<hexastorm> so that would mean it would require a lot of logic but still might work..
<agg> 2*a would hopefully just shift a left by one, don't even need an adder, but a*b will take a bunch of logic depending on how wide they are
<hexastorm> great... and it would handle that multiplication in one "cycle"
<hexastorm> okay will see if I can get it on the chip...
jjeanthom has quit [Ping timeout: 256 seconds]
bvernoux has joined #nmigen
hexastorm has quit [Quit: Connection closed]
<lkcl> whoops he's gone already. most FPGAs have DSPs which implement straight multiply, the tools match against that. ah well.
<agg> lkcl: not the ice40hx4k they said they were using
<lkcl> agg: ahh :)
<lkcl> ouch, that'll be challenging
<lkcl> and interesting. long-multiplication FSM?
jjeanthom has joined #nmigen
richbridger has joined #nmigen
<modwizcode> I think the question is: will it actually generate the logic required given that there's no DSP
<modwizcode> I should know that answer but I can't remember
<modwizcode> It'd be really nice if the process of mapping in yosys was more clearly layed out somewhere
<modwizcode> there's a lot of mapping passes and things and it's not 100% clear to me how several are distinct
<whitequark[m]> * will generate a very slow comb multiplier, yes
peeps[zen] is now known as peepsalot
<modwizcode> Is it slow because it's not doing any optimizations?
<modwizcode> Or just because it's hard/impossible to do that well with in fabric logic
<modwizcode> I've been trying to find the implementation for that process in yosys but it's hard to track down
<whitequark[m]> comb multipliers have a long logic path
<modwizcode> oh I'm dumb, it can't do anything but a full comb tree in this case
<modwizcode> although wouldn't that still be an issue for a hard multiplier block?
<whitequark[m]> hardening logic greatly reduces overall overhead
<whitequark[m]> that said hard multipliers are often pipelined too
<modwizcode> I guess I wasn't aware of just how much difference you could make for hardening logic
<modwizcode> I don't deal with multipliers enough, is the pipelining just abstracted out into the timings for the DSP block?
<modwizcode> Actually how does that work at all...
<tpw_rules> no, you just give it values and it gives you a result n cycles later
<d1b2> <dub_dub_11> and you can (sometimes? usually?) tweak which pipeline regs get used to balance latency and speed
chipmuenk has quit [Quit: chipmuenk]
jjeanthom has quit [Ping timeout: 246 seconds]
revolve has quit [Read error: Connection reset by peer]
revolve has joined #nmigen