05:56 <sensille> but can arrays become distributed RAM, or do i always have to use Memory()?

19:25 <sensille> hm. a syncfifo with fwft=true fails to be mapped to bram (ecp5)

19:25 <whitequark[m]> use syncfifobuffered

19:26 <whitequark[m]> <sensille "but can arrays become distribute"> depends on the toolchain. using Memory will reliably do what you want, however

19:31 <sensille> ah, good, only one delay cycle in case it's empty

19:32 <sensille> i added an init vector to SyncFIFO to have it prefilled on startup. would that be a useful feature to add to the library?

19:36 <tpw_rules> i don't think that's a good idea because then the powerup state is different from the reset state

19:39 <sensille> great, *buffered works

19:41 <sensille> tpw_rules: good point. i don't use reset, but that might make it less useful for general purposes

19:43 <whitequark[m]> <sensille "i added an init vector to SyncFI"> I don't think this is generally useful enough, and supporting it with all permutations of FIFOs is tricky

19:48 <sensille> ok

21:49 <kbeckmann> what would be a good way to write a testbench for a design that is written in nMigen but also uses verilog modules (that i want to include in the test)? would cxxrtl be able to do this? or should i export the whole design to verilog and run e.g. verilator or iverilog?

21:54 <whitequark[m]> cxxsim will do it at a later point

21:54 <whitequark[m]> for the time being, please use some other ad-hoc solution

21:58 <kbeckmann> alright, thanks for the answer :)