whitequark[m] changed the topic of #nmigen to: nMigen hardware description language · code https://github.com/nmigen · logs https://freenode.irclog.whitequark.org/nmigen
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<_whitenotifier-5> [YoWASP/nextpnr] whitequark pushed 1 commit to develop [+0/-0/±1] https://git.io/JYAQS
<_whitenotifier-5> [YoWASP/nextpnr] whitequark ee70ca0 - Update dependencies.
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<sensille> i could use some help with pypy. i managed to install pypy3.7 (from source, thanks debian). do i now have to rebuild anything from the nmigen toolchain, or reinstall it? at least pypy hasn't any knowledge of nmigen yet
<sensille> or is it just a matter of adjusting pypys library path?
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<whitequark[m]> you need to use pypy's pip i think
<sensille> ok, i runs with in a virtualenv, but with pypy it's significantly slower than with python itself :-/
<sensille> *it
<sensille> strange
<sensille> a simple benchmark show pypy 50 times faster than python, but simulation for my module takes twice as long
<whitequark> are you reusing a simulator?
<whitequark> i.e. create Simulator() once, then reset() it for every unit test
<sensille> no, single use
<whitequark> that means that the JITted code most likely gets dropped and recreated for every test
<whitequark> if the tests don't run a lot of logic, this could slow it down significantly
<sensille> just one run, one test. a long test
<whitequark> oh, hm.
<whitequark> and is that your entire test suite?
<sensille> currently, yes. just a fuzzing test
<sensille> but i had to build nearly everything from source. something might be off somewhere
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<slan> sensille: Could you post your benchmark? I just ran my own test with pypy and it's slightly slower that cpython (installed from binary)
<sensille> slan: i run this: https://djfk.net/movequeue.py
<sensille> haven't tried to boil it down yet
<sensille> also i haven't tried cpython
<sensille> what is the intended way to end a simulation on failure? raise?
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<sensille> wow, finally found the bug in the design. it never fails to astonish me how hard it is to write good tests
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<hexastorm> Hey all, I have a created a project which allows you to control a 3D printer with nmigen. CNC machine is already moving see https://youtu.be/-0uB2MydtrE
<hexastorm> There is a lot to be improved.. but as far I know.. this is the first working core :-)
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<sensille> hexastorm: nice, i'm working on the same :)
<hexastorm> I am interested.. do you have code to share?? my code is here https://github.com/hstarmans/FPGAG/blob/master/src/FPGAG/core.py
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<whitequark> hexastorm: very nice!!
<hexastorm> My code works as follows;
<hexastorm>   -- SPI command interface (copied from luna)
<hexastorm>   -- transactionalized FIFO (copied from luna)
<hexastorm>   -- SPI parser (basically an extension of SPI command interface)
<hexastorm>   -- Dispatcher --> dispatches signals to actual hardware
<hexastorm>   -- Polynomal integrator --> determines position via integrating counters (shift registers)
<hexastorm> Thanks.. hope I can get it as clean as the code from nmigen / luna
<sensille> hexastorm: i have several version, currently my board runs klipper. an earlier version, also polynomial based is here: https://github.com/sensille/conan/blob/master/3dpfs.srcs/sources_1/new/motion.sv
<sensille> i just started to move to nmigen, though
<sensille> regarding the polynomial approach we can definitely share ideas
<hexastorm> I couldn't implement bezier as I don't have a multiplier on my ICE chip
<sensille> one of the early tests https://youtu.be/BJUyOK3UBNs
<sensille> i do bezier with adders
<hexastorm> I thought about but with position feedback adders are harder or not?
<hexastorm> the multiplication approach just gives you the position using casteljau giving a few points
<hexastorm> a limitation of my approach is that you have to send coefficient for a segment and the number of ticks in that segment
<hexastorm> this ticks is uniform for all motors..
<sensille> yeah, we're doing somewhat the same :)
<hexastorm> max ticks is now 10_000...
<hexastorm> polynomal is a seperate module.. also has a test suite see https://github.com/hstarmans/FPGAG/blob/master/test/FPGAG/test_virtual.py
<hexastorm> it is quite easy to extract..
<hexastorm> one of the issues I still have is that nmigen works with yield from syntax and my regular python functions do not use yield from syntax
<hexastorm> as a result I have duplicate controller classes... which is quite ugly
<sensille> also if you're interested in hardware: https://i.imgur.com/nPuYwNb.jpg
<sensille> but you probably want to make your own board :)
<hexastorm> well it is a lot of work.. prefer to stand on the shoulders of giants .
<hexastorm> my focus is on laser scanning and I like to have a link with a raspberry
<sensille> not giant here, but i could probably make you one, i still have some PCB
<hexastorm> it is very nice.. does it have hardware multipliers?
<sensille> yes, ecp5 45k
<sensille> 6 stepper drivers on board
<hexastorm> well that is a lot better...
<sensille> the really interesting part is how to get splines from the 3d model
<hexastorm> yes I know...
<hexastorm> there are a lot of challenges...
<sensille> just years of work ahead
<hexastorm> well.. I am interested.. my main focus is on laser scanning
<hexastorm> I will integrate this project with my CNC FPGA code, see https://github.com/hstarmans/hexastorm
<hexastorm> so your board would only be usefull if I have some pins to connect my laser module
<sensille> what do you need for laser scanning?
<sensille> the board has endless ways to connect
<hexastorm> scanhead pcb needs 12V, SDA connection to set laser voltage, pulse for mirror motor, pulse for two laser channels and pulse read out of photodiode
<hexastorm> your conan boards is real nice .. is it open hardware? Did you name it after conan the barbarian?
<sensille> just a name i couldn't get out of my head
<hexastorm> nice.. why are you building it ?
<sensille> because i want an fpga based printer :)
<hexastorm> I need the FPGA as I need accuracy beyond 10 micron..
<sensille> nice. yeah, it makes much more sense for that :)
<hexastorm> my code should work on your board... luna has a usb controller..
<hexastorm> do you also have a microcontroller?
<sensille> i'm not 100% what your pitch is selling me, laser scanning or printing?
<sensille> yes, a small stm32f0
<hexastorm> the pitch is selling the use of prism... this is used nowhere at the moment..
<hexastorm> main issue is that the pitch is mostly selling "technology" and markets where this technology this is used..
<hexastorm> anyhow you can use a prism for laser scanning and printing..
<hexastorm> my current circuitry only supports "printing" ..
<hexastorm> worked on this for 7 years :P ... so guess I am biased
<sensille> wow
<hexastorm> yep it is almost sad... as long as it took..
<hexastorm> dutch state is also still funding this line of reseach https://www.amsystems.nl/
<hexastorm> but focussed on a plurality of bundles..
<hexastorm> there are applications also in laser induced forward transfer etc.. but the main thing I need is a working setup where I can reliable expose a substrate..
<hexastorm> if this is programmed in python with nmigen and easy to read .. it might convince a lot of people to explore it
<hexastorm> anyhow sensille, I would try to copy part of my codes or start from it..  it is more work than you think.. also I am curious which parts you do not like
<hexastorm> I am off.. gonna hack on :-)
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* lkcl waves to whitequark.
<whitequark[m]> hi
<lkcl> am just about to embark on a rather... hurried (tape-out deadline apr 12th) use of cxxrtl to do ASIC simulation, based on that really good tutorial
<lkcl> there will be *three hundred* vhdl components to pull in :)
<whitequark[m]> good luck
<lkcl> there's no rush: i had a suggestion / idea for the yosys cxxrtl
<lkcl> yeah lol :)
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<whitequark[m]> which idea?
<lkcl> to have it output separate .h and .cpp files rather than the struct be a part of the cpp file
<lkcl> in future
<lkcl> or, is there an option to write_cxxsim to already do that?
<lkcl> #include "blink.cpp" is fine for small designs. when there's 300 and it's expected to produce a 200mb binary that's a leetle big :)
<lkcl> i can write a temporary hack/extractor to split out the struct
<whitequark[m]> there is an option, please see the help text
<lkcl> ahh fantastic!
<lkcl> wheww :)
<lkcl> ok back to focussing on seriously tight deadlines
<lkcl> thanks whitequark[m]
<whitequark[m]> np
<lkcl> ah that's interesting. a 12-bit counter works uint32_t counter = top.p_counter.get<uint32_t>();
<lkcl> but a 4-bit value does not (compile error)
<lkcl> nope. my stupid mistake. doh
<lkcl> works perfectly
<lkcl> in case anyone's interested, we've an ASIC to test via JTAG.
<lkcl> but before getting there, the RTL (nmigen, litex) needs testing before it goes into the P&R tool
<lkcl> coriolis2 happens to use a subset of VHDL for its cells, so after P&R that VHDL can be put *back* into the exact same simulation... and tested to make sure it's the same as the nmigen original
<lkcl> so the plan is: write a cxxrtl unit test that back-ends JTAG into the openocd "jtagremote" protocol
<lkcl> then connect to *all three* cxxsim simulations using openocd JTAG
<whitequark> this is the kind of thing cxxrtl has been developed for
<d1b2> <4o> connect simulations using openocd?
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<lkcl> 4o: yes
<lkcl> dang it actually works
<d1b2> <4o> like pass signals from one sim to another?
<lkcl> 4o: openocd has a built-in module called "jtagremote". that's enabled with this: https://git.libre-soc.org/?p=soc-cxxrtl-sim.git;a=blob;f=small_jtag_test/openocd.cfg;hb=HEAD
<lkcl> actually i did do that, once :)
<lkcl> it was horribly slow but functional (due to TCP socket polling)
<lkcl> one nmigen simulation using openocd jtagremote as "client", the other as "server"
<lkcl> whitequark: it's pretty damn easy. really impressed.
<whitequark[m]> :)
<lkcl> 4o: here's the actual socket read/write, which is the protocol that openocd "remote_bitbang" interface understands
<lkcl> https://git.libre-soc.org/?p=soc-cxxrtl-sim.git;a=blob;f=small_jtag_test/main.cpp;h=e153d76436ccc15d422bb8fa394ac93934ead763;hb=1feb11642ab3f8d1cdc350ff3027bacf9434a4d7#l82
<lkcl> does "top.p_tck.set<bool>(((c - '0') >> 2) & 1);" and so on and... err... that's it
<FL4SHK> any way I could get my `Packarr` class into nMigen?
<FL4SHK> There's a `PackedStruct` class coming later, right?
<FL4SHK> I'd like to have my `Packarr` class support having members that are `PackedStruct`s
<FL4SHK> as well as have `Packarr`s that are within `PackedStruct`s
<FL4SHK> right now, I've just got an element width inside of the `Packarr` class
<whitequark[m]> that's something to discuss during the design cycle of `PackedStruct`
<FL4SHK> I see
<whitequark[m]> we're not there yet, though we'll be there soon
<FL4SHK> It'd be really cool to be able to do `my_packarr[index].packed_struct_element`
<FL4SHK> I'll be sticking around
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<lkcl> whitequark[m]: oo, err... whoops :)
<lkcl> c/litex/florent/libresoc.v:203205$14464'.
<lkcl> Segmentation fault
<lkcl> Cleaned up 4501 empty switches.
<lkcl> make: *** [ls180.cpp] Error 139
* lkcl will spend some time tracking down why yosys segfaults, there
<whitequark[m]> take a look at the bugpoint pass
<whitequark[m]> in case you need to reduce the testcase
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<lkcl> 0x0000000000dd3d8c in (anonymous namespace)::CxxrtlWorker::dump_module_intf(Yosys::RTLIL::Module*) ()
<lkcl> sorry, i'm not hugely familiar with this (diving in cold), i'm assuming the bugpoint pass is a yosys command, see how far i get
* lkcl needs to rebuild yosys with -g
<lkcl> This command minimizes the current design that is known to crash Yosys with the
<lkcl> given script into a smaller testcase.
<lkcl> nice!
<lkcl> hmmm...
<lkcl> ERROR: Assert `is_valid_clock(signal)' failed in backends/cxxrtl/cxxrtl_backend.cc:2280
<lkcl> Demoting introduced module ports.
<lkcl> Simplifications exhausted.
<whitequark[m]> might have to fiddle with options a bit or reduce manually
<lkcl> ohhh i know what i did. ha. i was experimenting with cocotb
<lkcl> replacing sys_clk with "always #100 sys_clk = ~sys_clk"
* lkcl will put sys_clk back into the design, now :)
<lkcl> hmmm still messed up after correcting
* lkcl needs more investigating
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<lkcl> whitequark[m]: got it
<lkcl> and that's with yosys... Yosys 0.9+4008 (git sha1 049e3abf, clang 9.0.1-12 -fPIC -Os)
<lkcl> ahh i bet it's this:
<lkcl> reg [32:0] thing [15:0];
* lkcl just uploaded a simpler case, removing the conditional test
<lkcl> even simpler
<lkcl> reg thing[15:0]
<lkcl> and still a segfault
<sensille> funny, with nmigen i find myself using much more combinatorial logic
<FL4SHK> I'd really like a feature similar to a VHDL `variable`
<FL4SHK> that'd make implementing something like a VHDL `function` easier
<FL4SHK> you have to have a separate signal for every calculation as things stand today
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<lkcl> whitequark: ah ha! if i run proc followed by memory, that example is "fine"
<lkcl> yyep, that "fixes" the problem even with the larger design (full ls180.v)
<lkcl> 60 _thousand_ lines of cxxsim simulation output lol
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<lkcl> llvm-9 is up to 2gb resident memory trying to compile it, teehee
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<FL4SHK> so I need `Packarr.__getitem__()` to not always return `word_select()`
<FL4SHK> depending on the shape
<FL4SHK> though I suppose you could just do this stuff manually for now
<FL4SHK> I don't know how to do it
<FL4SHK> I need to maintain type information about the elements of the packarr
<FL4SHK> And other than using a shape, I don't know
<FL4SHK> I'm trying to construct a precursor to what would actually be brought into nMigen
<FL4SHK> whitequark[m]: ^
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<vup> FL4SHK: do the element of your packarr all have the same type?
<FL4SHK> vup: yes
<vup> hmm yeah, that seems pretty hard to do atm
<vup> I guess the opposite of the as_value of ValueCastable would be needed
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