00:29 <_whitenotifier-5> [YoWASP/nextpnr] whitequark pushed 1 commit to develop [+0/-0/±1] https://git.io/JYPJh

00:29 <_whitenotifier-5> [YoWASP/nextpnr] whitequark 84223f7 - Update dependencies.

06:33 <sensille> is there a documentation for the parameters to verilog.convert?

06:40 <sensille> and how do i add a record to the ports list?

06:51 <sensille> ok, by guessing through the source i got: mybus.as_value().parts. is that the official way?

08:46 <d1b2> <4o> https://github.com/nmigen/nmigen/blob/c84d4aff6ef62ebf7f06728bd04754bc298fddca/nmigen/back/verilog.py#L59 -> https://github.com/nmigen/nmigen/blob/c84d4aff6ef62ebf7f06728bd04754bc298fddca/nmigen/back/rtlil.py#L1052 -> https://github.com/nmigen/nmigen/blob/c84d4aff6ef62ebf7f06728bd04754bc298fddca/nmigen/hdl/ir.py#L526

08:47 <d1b2> <4o> that should be the full list of args for verilog.convert

08:48 <sensille> thanks

13:47 <sensille> what is the best way to force a signal into the vcd under a meaningful name? the signal in question is an array of Signal(32)

13:48 <agg> Signal(32, name=f"sig{x}")

13:54 <sensille> nice. so i should make it a habit to name all state variables

14:06 <agg> They all get named by their python variable name automatically if you don't set a name

14:06 <sensille> unless it's an array?

14:06 <agg> So like "ctr = Signal(4)" will be called ctr, but "a = [Signal() for _ in range(4)]" doesn't have a name for each signal so they don't get named

14:07 <agg> So only need to set the name if it can't work it out automatically or for instance you want to put extra info in the name

14:08 <agg> eg if I'm looping over something I might want the actual key in the signal name instead of them all being the same but with $1, $2, etc after them

14:11 <sensille> makes sense