<lkcl>
whitequark: was "z" (or was it "x") added to nmigen yet? i vaguely recall some discussion 18 months ago about that
<whitequark[m]>
you'll have to be more specific on what you want
<lkcl>
it wasn't something i wanted specifically, i just have a very vague recollection that for some reason "z" and "x" came up when we discussed nmigen for ASIC use
<lkcl>
it was ages ago so i can't recall exactly what it was about
<whitequark[m]>
neither do i
<lkcl>
:)
<lkcl>
it will come back to me in a day
<lkcl>
btw one thing we do need is that SIMD partitioning
<lkcl>
awygle very kindly agreed to help write up an RFC
<lkcl>
except we haven't heard from him in a while
<whitequark[m]>
to me this feels like something that should live outside of the core language, so the RFC should cover the extensibility mechanisms that would be useful for implementing it
<lkcl>
yes. basically it boils down to doing pretty much exactly the same thing as python operator.{insertthing} does
<lkcl>
Mux --> Value.mux
<lkcl>
Part --> Value.part
<lkcl>
Cat --> Value.cat
<lkcl>
(and corresponding UserValue.xxx)
<lkcl>
and, from a readthrough of the code, because m.If (etc) ultimately goes through to Value.cases which in turn use Mux, Part, and Cat
<whitequark[m]>
mm that's kind of weird but maybe reasonable, would have to think a bit about it
<lkcl>
that's basically all we need
<lkcl>
we can get a heck of a long way and it's actually extremely powerful
<whitequark[m]>
i'm planning to do a maintenance release soon and then we can make a proper roadmap
<lkcl>
things like a ComplexNumberSignal or a FixedPointSignal could be defined
<whitequark[m]>
a release is quite overdue
<lkcl>
i did wonder :)
<whitequark[m]>
<lkcl "things like a ComplexNumberSigna"> as long as these are based on UserValue that seems quite reasonable
<whitequark[m]>
well, ValueCastable now
<lkcl>
yehyeh that's the idea... oh right, nice, that all went through
<whitequark[m]>
cool
* lkcl
deep breath, apologies, 2am here. pushing my luck being up this late
<whitequark[m]>
looking forward to the RFC then
* lkcl
nods. night
<whitequark[m]>
night!
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<kbeckmann>
another ASIC question... is it possible to create ROM by using Memory() and only use a read port?
<kbeckmann>
i realize that ideally i should use a fab-specific block for both ROM and RAM, but in this case i just want a handful of bytes for ROM like a version string or a look up table for a font etc.
<gatecat>
kbeckmann: yes, Yosys should map a ROM like this to logic automatically
<kbeckmann>
thanks!
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<lkcl>
kbeckmann: we had some ahh interesting experiences with yosys / SRAMs
<lkcl>
Chips4Makers[m] helped out, to create a custom 4k block for us, which we had to declare as a yosys "blackbox"
<lkcl>
(we put it behind a wishbone classic interfac)
<lkcl>
but because that's so new (custom written) we did a "safe" thing of adding some 128 byte and 256 byte nmigen-declared SRAMs
<lkcl>
which yosys, for lack of access to an actual memory, turns into DFFs
<lkcl>
and holy s*** does it eat silicon area
<lkcl>
those DFFs are so many and so densely packed that Jean-Paul from LIP6.fr (author of coriolis2) has had to add some extra clocktree fan-out repeaters
<lkcl>
also we are a bit concerned about power / heat so may have to end up splitting the DFF groups into two, laid out in different locations on the ASIC
<kbeckmann>
ah that's interesting. yeah it takes up so much space. i can barely fit 64 bytes in the 300x300 um that i am working with right now.
<kbeckmann>
just tried out the ROM memory thing and it seems it all gets optimized away, trying to figure out where that happens.
<lkcl>
are you running "flatten"? we had to switch that off
<lkcl>
we experimented with "partial" flatten. giving a list of leaf-nodes (modules) that we wanted flattened, and leaving the rest
<lkcl>
the only problem with that being that if you didn't connect up all the ports (or connected some modules to constants), they were either left hanging or were *not* properly optimised out. sigh
<lkcl>
Jean-Paul had fun dealing with that one, because coriolis2 expected the netlist to be clean / fully-connected :)
<lkcl>
my general reaction to a year's worth of experiences doing ASIC layout can be summarised as:
* lkcl
aaaaaaaaaaa!
<lkcl>
:)
<kbeckmann>
thanks, will see if flatten is somehow enabled. the tools do a lot of stuff automatically :).
<lkcl>
yehyeh
<lkcl>
we don't use OpenLANE / OpenROAD btw, because (a) we started before that was set up and (b) you can't do the IOpads yourself under the Skywater 130nm Programme.
<lkcl>
btw, Chips4Makers[m] is going to be doing a port of FlexLib cell libraries (standard cells, IO pads, SRAM generator) to Skywater 130nm PDK.
<lkcl>
that will allow anyone to do *full* (complete) skywater ASIC, without needing the "Management Core"
<kbeckmann>
ah i see. regarding iopads, you now have the option to do an analog design with raw access to the pads.
<lkcl>
ahhh
<lkcl>
that's new
<lkcl>
now i'm interested
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<kbeckmann>
it's called caravan instead of caravel
<lkcl>
can i ask: where's the applications process?
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<lkcl>
lol
<kbeckmann>
you might want to watch the last efabless video about the openmpw two walkthrough. applications go via efabless.com iirc. also sorry for the asic takeover in this channel, think we are straying a bit off topic now :)
<lkcl>
got it, thx
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<kbeckmann>
oops, turns out the Memory ROM issue i had was because i had connected my wires incorrectly so it got optimized away as it should. seems to work properly now.
<lkcl>
whoops, been there :)
<d1b2>
<dub_dub_11> > it's called caravan instead of caravel Presumably this different thing isn't under the same sponsored-by-google deal?
<lkcl>
don't know. i can find caravel under efabless git, but not caravan.
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<FL4SHK>
Arrays of records on the equivalent of "ports" would be nice to have in nMigen
<FL4SHK>
I might use pyhdlgen for that specific feature
<whitequark[m]>
arrays of records work
<whitequark[m]>
try it
<FL4SHK>
well, I'm aware that arrays of records in general work
<FL4SHK>
or do arrays of records as "ports" work?
<whitequark[m]>
what are "ports" here?
<FL4SHK>
I know nMigen doesn't have ports but
<whitequark[m]>
what do you actually want
<FL4SHK>
oh wait, I remember what the problem was
<FL4SHK>
the problem was that I couldn't do `.eq` to an Array
<FL4SHK>
My bad
<whitequark[m]>
Cat() it first, perhaps?
<FL4SHK>
That works
<FL4SHK>
Can you do `Cat(array)`?
<FL4SHK>
as in
<FL4SHK>
`array` is the name of the signal
<whitequark[m]>
of the signal?
<FL4SHK>
Yeah, just the whole signal
<FL4SHK>
I don't want to have to do `Cat(array[0], array[1])`
<whitequark[m]>
an array is not a signal, but what you wrote works, try it
<FL4SHK>
cool
<FL4SHK>
can you stick an array inside of a `Record`?
<whitequark[m]>
not really
<FL4SHK>
That sounds like a limitaiton
<whitequark[m]>
perhaps
<whitequark[m]>
there is a reason for it
<whitequark[m]>
records are values, arrays are not
<whitequark[m]>
arrays can contain anything at all
<FL4SHK>
Any plans for something that'd work for putting an array of records inside of another record?
<FL4SHK>
Not necessarily storing an `Array` within a `Record`
<whitequark[m]>
not presently, but it's a possibility in principle
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<Sarayan>
whitequark: I'm trying to understand but I'm a little lost, how many fpga i/os a block of 8 i/os in the glasgow require?
<whitequark[m]>
16
<Sarayan>
only? With input, output, direction control, voltage control?
<whitequark[m]>
please look at the schematic to see how it works
<Sarayan>
Part of being a little lost is that I'm not finding the schematic in the github :-)
<whitequark[m]>
also this is #nmigen and not #glasgow
<Sarayan>
ah sorry
<Sarayan>
-ETOOMANYCHANNELS
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<kbeckmann>
(sorry for off-topic) @dub_dub_11, lkcl: regarding caravan, it's the -an analog version of caravel. the sources were published just an hour ago so it's some really new stuff. it was announced in the #analog-design channel in the skywater-pdk slack together with the caravel_user_project_analog base project.
<d1b2>
<dub_dub_11> Oh, awesome! I will ask more about it somewhere a little more suitable 😄
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<lkcl>
kbeckmann, ah excellent. still not relayed through to the #skywater-pdk though
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