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<kbeckmann>
is there anything i should be very careful with when using nmigen for ASICs? i'm considering using nmigen for a skywater 130/efabless project and so far it seems to work fine with the simulations i've done. i know that reset is mandatory, that registers and memory can't be initialized. are there other things i should know about?
<whitequark[m]>
you might encounter issues with negative polarity reset
<whitequark[m]>
but they shouldn't be show-stoppers
<whitequark[m]>
that's all i can think of
<kbeckmann>
okay good to know. in this case, the reset is controlled via a management risc-v core so i should be able to use any polarity through firmware. does negative polarity reset mean that the design is held in reset when reset is low?
<whitequark[m]>
yeah
<kbeckmann>
thanks
<kbeckmann>
just wanted to confirm.
<whitequark[m]>
right now there's no direct support for that, you have to put an inverter somewhere
<kbeckmann>
ok that i can do. i instantiate the nmigen design through a verilog wrapper
<whitequark[m]>
if you don't directly drive reset from a pin it probably just doesn't matter what you do
<kbeckmann>
i guess i could register it through a clock just to be safe?
<kbeckmann>
as in "always @(posedge clk) nmigen_rst <= ~rst;"
<whitequark[m]>
the primary reason you might want an active low reset is so that during power rampup your circuit is held in reset and doesn't glitch
<whitequark[m]>
but if everything is controlled by a management core it doesn't matter
<whitequark[m]>
that's how i see things here, anyway
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<kbeckmann>
ah that makes sense, haven't thought about that at all. i guess that's one the reasons inverted control signals are so common.
<whitequark[m]>
yeah. i've hit some issues with these on Glasgow
<whitequark[m]>
though in the other direction. the FPGA has pullups
<whitequark[m]>
basically you want the "default" state to be a nop
<whitequark[m]>
or a safe state or something like that
<_whitenotifier-3>
[nmigen-boards] vmunoz82 opened pull request #153: panologic g2 board support added - https://git.io/J39lh
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