<_whitenotifier-3>
[nmigen-boards] hansfbaier synchronize pull request #152: add board support for QMTech XC7A35T core board and daughterboard - https://git.io/J3L4k
<_whitenotifier-3>
[nmigen-boards] hansfbaier commented on pull request #152: add board support for QMTech XC7A35T core board and daughterboard - https://git.io/J3ZWd
<_whitenotifier-3>
[nmigen-boards] hansfbaier edited a comment on pull request #152: add board support for QMTech XC7A35T core board and daughterboard - https://git.io/J3ZWd
emeb has left #nmigen [#nmigen]
<_whitenotifier-3>
[nmigen-boards] whitequark commented on pull request #152: add board support for QMTech XC7A35T core board and daughterboard - https://git.io/J3ZlL
<_whitenotifier-3>
[nmigen-boards] hansfbaier commented on pull request #152: add board support for QMTech XC7A35T core board and daughterboard - https://git.io/J3Z84
<_whitenotifier-3>
[nmigen-boards] hansfbaier edited a comment on pull request #152: add board support for QMTech XC7A35T core board and daughterboard - https://git.io/J3Z84
vnksnkr has joined #nmigen
roamingr1 has joined #nmigen
vnksnkr has quit [Ping timeout: 276 seconds]
revolve has quit [Read error: Connection reset by peer]
roamingr1 has quit [Ping timeout: 240 seconds]
roamingr1 has joined #nmigen
revolve has joined #nmigen
roamingr1 has quit [Ping timeout: 268 seconds]
hell__ has quit [*.net *.split]
lethalbit has quit [*.net *.split]
lethalbit has joined #nmigen
hell__ has joined #nmigen
Bertl_oO is now known as Bertl_zZ
pftbest has joined #nmigen
sensille has joined #nmigen
jjeanthom has joined #nmigen
pftbest has quit [Remote host closed the connection]
_whitenotifier-3 has quit [*.net *.split]
pftbest has joined #nmigen
_whitenotifier-3 has joined #nmigen
pftbest has quit [Remote host closed the connection]
pftbest has joined #nmigen
revolve has quit [Ping timeout: 252 seconds]
revolve has joined #nmigen
<_whitenotifier-3>
[nmigen-boards] hansfbaier commented on pull request #152: add board support for QMTech XC7A35T core board and daughterboard - https://git.io/J3cBG
<_whitenotifier-3>
[nmigen-boards] whitequark commented on pull request #152: add board support for QMTech XC7A35T core board and daughterboard - https://git.io/J3cVS
pftbest has quit [Remote host closed the connection]
pftbest has joined #nmigen
<_whitenotifier-3>
[nmigen-boards] hansfbaier commented on pull request #152: add board support for QMTech XC7A35T core board and daughterboard - https://git.io/J3cXo
pftbest has quit [Remote host closed the connection]
pftbest has joined #nmigen
Bertl_zZ is now known as Bertl
<FL4SHK>
what is an acceptable amount of assertions that you have the right kind of AST node for my project?
<FL4SHK>
actually
<FL4SHK>
I think ti's better not to ask a loaded question like that
Bertl is now known as Bertl_oO
pftbest has quit [Remote host closed the connection]
lmp has joined #nmigen
lmp has quit [Quit: Connection closed]
pftbest has joined #nmigen
revolve has quit [Read error: Connection reset by peer]
revolve has joined #nmigen
jjeanthom has quit [Ping timeout: 265 seconds]
jjeanthom has joined #nmigen
mindw0rk_ has joined #nmigen
mindw0rk has quit [Ping timeout: 268 seconds]
mindw0rk_ is now known as mindw0rk
pftbest has quit [Remote host closed the connection]
pftbest has joined #nmigen
jjeanthom has quit [Ping timeout: 240 seconds]
<lkcl>
has anyone any ideas on how to pull a reset signal on *just one* module?
<lkcl>
preferably without creating an entire domain to do so
chipmuenk has joined #nmigen
<tpw_rules>
you can wrap it in a ResetInserter
<FL4SHK>
decided to continue with what I was doing for assertions
<FL4SHK>
I do some asserts to make sure you've got the right kind of AST Node
<FL4SHK>
but it's not completely perfect
<FL4SHK>
some of it allows invalid VHDL
<FL4SHK>
is that a problem if the VHDL implementation catches it?
modwizcode has quit [Ping timeout: 260 seconds]
<lkcl>
tpw_rules: fantastic, thank you
<lkcl>
are there any examples anywhere of how to use ResetInserter?
pftbest has quit [Remote host closed the connection]
pftbest has joined #nmigen
pftbest has quit [Remote host closed the connection]
pftbest has joined #nmigen
<lkcl>
tpw_rules: thank you, works great.
mithro has quit [Ping timeout: 245 seconds]
mithro has joined #nmigen
esden has quit [Ping timeout: 260 seconds]
_florent_ has quit [Ping timeout: 246 seconds]
mithro has quit [Excess Flood]
davidlattimore has quit [Ping timeout: 260 seconds]
mithro has joined #nmigen
_florent_ has joined #nmigen
davidlattimore has joined #nmigen
lsneff has quit [Ping timeout: 250 seconds]
ianloic_ has quit [Ping timeout: 258 seconds]
tannewt has quit [Ping timeout: 245 seconds]
tcal has quit [Ping timeout: 248 seconds]
guan has quit [Read error: Connection reset by peer]
esden has joined #nmigen
guan has joined #nmigen
lsneff has joined #nmigen
Qyriad has quit [Ping timeout: 258 seconds]
tannewt has joined #nmigen
tcal has joined #nmigen
ianloic_ has joined #nmigen
Qyriad has joined #nmigen
<vup>
FL4SHK: that probably depends on the quality of error messages you want to provide, I can imagine errors coming from the VHDL implementation being harder to understand than the ones you generate yourself...
chipmuenk has quit [Quit: chipmuenk]
<FL4SHK>
vup: the project I'm working on has you writing VHDL code from within Python
<FL4SHK>
well, you're generating a VHDL AST
<FL4SHK>
then my tool will translate it into real VHDL
<FL4SHK>
so I don't know
<FL4SHK>
implementing VHDL-side errors themselves seems hard
<vup>
what do you mean by VHDL-side errors?
<FL4SHK>
errors that the VHDL implementation could catch for me
<FL4SHK>
I'd basically be making a partial VHDL implementation regarding errors
<vup>
yeah, I mean that kind of seems unavoidable with your project
<vup>
its a matter of where you want to draw the line I guess
<FL4SHK>
I'm not going to be doing VHDL type checking
<FL4SHK>
I could make it a long term goal
<FL4SHK>
I do some error checking
<vup>
if the structure of the python code and the vhdl code will be very similar, it could be the case that you don't even need any error checking on the python side, but to me it sounds like you want to write more of a meta programming layer for VHDL, so for example just finding the correct piece of python code to look at, when you get a error message from the VHDL implementation could start to get difficult.
<FL4SHK>
vup: so I planned on letting you see the Python line numbers within the VHDL
<FL4SHK>
I have that set up already
<vup>
sure, but with one layer of python functions between that, that doesn't work anymore probably? Or you would need something like a complete stacktrace
<FL4SHK>
I am using the complete stacktrace to figure it out
<FL4SHK>
it's an argument to the VHDL AST nodes
<vup>
ok maybe what I said was imprecise, what I mean is, there is not always a correct entry of the stacktrace to use.
<FL4SHK>
why would that be the case?
<FL4SHK>
I take the exact source code position to use within the stacktrace
<vup>
say you are writing a function that takes some arguments and then generates some AST nodes from that
<vup>
do you want to get the point in the function where the AST node was generated, or the point where the function was called?
<FL4SHK>
I provide the point where the AST node was generated
<vup>
I would say, it depends, for some errors you want to get the point in the function, for some you want the place where the function was called (for example if the error only occurs for a specific set of arguments)
<FL4SHK>
I don't know how I'd track that
<FL4SHK>
I thought tracking the location of AST nodes would just work (TM)
<vup>
I mean the python stacktrace give you the whole stacktrace, does it not? So in principle it should be possible to track, but of course printing the whole stacktrace for every AST node would get very unreadable aswell
<FL4SHK>
I think it's good to be able to see the line that an AST node was generated on
<FL4SHK>
even if it's not the perfect answer
<FL4SHK>
I see your point
<FL4SHK>
here's the thing
<FL4SHK>
I don't print out a whole stack trace
<vup>
yes, I understood that, I am saying always printing out the whole stack trace would not be much better
<FL4SHK>
I don't always print the whole stack trace
<FL4SHK>
I don't print it out at all
lf_ has joined #nmigen
lf has quit [Ping timeout: 276 seconds]
revolve has quit [Ping timeout: 240 seconds]
revolve has joined #nmigen
pftbest has quit [Remote host closed the connection]
pftbest has joined #nmigen
pftbest has quit [Read error: Connection reset by peer]