Lofty changed the topic of #prjmistral to: Project Mistral: Yosys (and hopefully nextpnr) on Cyclone FPGAs - https://github.com/ZirconiumX/mistral - logs: https://freenode.irclog.whitequark.org/prjmistral
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<Sarayan> Yesss, I'm cycling all 7 formats
<Sarayan> cycling = load options/cff/cram from a bitstream, then save it again
<Sarayan> which means I'm managing all the framing, the checksums, etc
<Sarayan> time to get back to the contents I guess now :-)
<Lofty> That's excellent news, Sarayan
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<Sarayan> what is a "jtag bsr"?
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<daveshah> Boundary scan register?
<jevinskie[m]> Awesome! I think people often call that “round tripping” for toolchains
<Sarayan> Ah probably, tahnks
<awygle> nice job Sarayan!
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<Sarayan> hmmm, and any idea what "RPI
<Sarayan> hmmm, and any idea what "RPI" could mean?
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<awygle> rochester polytechnic institute
<sorear> I’m missing the context but it could also be Rensselaer
<Sarayan> cyclonev internal names is the context
<Sarayan> RPI_FCL_DB, RPI_BIT_ADDRESS, RPI_RE_NODE, RPI_ATOM_TYPE, RPI_PORT_TYPE, etc
<Sarayan> SIMPLE_RPI_CACHE too
<awygle> Row Packet Index? no idea'
<awygle> sorear did my joke better than i did
<awygle> i always get that wrong
<sorear> I just always assume people are talking about azonenberg’s school
<Sarayan> according to google it's raspberry pi, which doesn't help :-)
<awygle> i was, i just always call it rochester
<awygle> even though it's in albany