Lofty changed the topic of #prjmistral to: Project Mistral: Yosys (and hopefully nextpnr) on Cyclone FPGAs - https://github.com/ZirconiumX/mistral - logs: https://freenode.irclog.whitequark.org/prjmistral
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<Sarayan> hey guys, any guess about what PLLGLOBALDRV_CNRA could mean?
<Sarayan> PLL global drive sure, but CNRA?
<Sarayan> it's another output from the pll that can go to the sector clock wtihout going through the other clock networks
<Sarayan> everything else goes through gclk or qclk
<Sarayan> ok, there's CNRB too
<sorear> clock network routing or something
<mwk> corner?
<Sarayan> ahhh could be
<Sarayan> PLLMOUT0 -> PLLLCORNER_MCNT -> GCLKMUXFDBK_ENA_2_RE -> PLLGLOBALDRV_CNRA
<Sarayan> RE = Routing Element
<Sarayan> so it seems connection to the M counter
<Sarayan> connected
<Sarayan> -> GCLKFB actually.... feedback?
<mwk> sounds reasonable
<mwk> as in, PLL feedback
<Sarayan> yeah, other parts of the doc confirm that, cool
<jevinskie[m]> Anyone reach out to Gregg like he requests in the debug strings? :P https://www.linkedin.com/in/gregg-baeckler-3771439/
<jevinskie[m]> Oh cool I didn’t notice that the developers get a personalized ASCII art banner, I need to print those out :)
<Lofty> I didn't know it was specifically him :P
<jevinskie[m]> libsynth_opt has rtl_whoami which associates version control usernames with first names and ascii art banners :)
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