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<Sarayan>
Interesting design: all connections to a routing line are done in one point, on a very small rectangle (like 4x2, 4x2, that kind of size) of bits in the 2d firmware. Which means there's only one driving spot on evey metal line
<Sarayan>
then there's multiple connections downstream of course. It's all 1:n
<Lofty>
I guess that's one way of avoiding multiple drivers
<Sarayan>
it's not n:m with a constraint of only one of the n active, there's really one one point
<Sarayan>
only
<Sarayan>
yeah
<Lofty>
I think Xilinx has something similar, but maybe daveshah or mwk could correct me there
<Sarayan>
on the spartan 2 I don't remember it being that obvious
<Sarayan>
that was "4x1, 4x2" incidentally
<Sarayan>
iirc the startan 2 was more single-mosfet connect-x-to-y all over the place
<mwk>
starting with virtex 2 / spartan 3, that's what the xilinx routing looks like as well
<mwk>
... mostly
<mwk>
there's also such a thing as long lines, which can be driven from one of 4 tiles