Lofty changed the topic of #prjmistral to: Project Mistral: Yosys (and hopefully nextpnr) on Cyclone FPGAs - https://github.com/ZirconiumX/mistral - logs: https://freenode.irclog.whitequark.org/prjmistral
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<chipb> bwidawsk: sorear: Lofty: yeah, for whatever reason the device database files are 'uuuuuge, particularly for the higher-end/new parts.
<chipb> I have no particular insight as to why that is.
<Lofty> Ouch
<chipb> could be inefficiency, could be flexibility in device characterization.
<chipb> I'd bet pro/std are not compatible schemas at this point either.
<chipb> I can pop on to the download portal if you wanted an estimate of a particular package.
<Sarayan> lite and pro seems to have domewhat differently designed databases
<Sarayan> somewhat
<Sarayan> phew, still so many things to do