Lofty changed the topic of #prjmistral to: Project Mistral: Yosys (and hopefully nextpnr) on Cyclone FPGAs - https://github.com/ZirconiumX/mistral - logs: https://freenode.irclog.whitequark.org/prjmistral
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<Lofty> The bitstream compression algorithm, if you hadn't already implemented it, Sarayan
<hansfbaier> ^ that sucks. What would it mean for the project?
<awygle> "wait til october", presumably
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<Sarayan> Lofty: Implemented ages ago, don't worry :-)
<Sarayan> it means nothing, we're not implementing a fpga
<Sarayan> we don't have the fifo, etc
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