Lofty changed the topic of #prjmistral to: Project Mistral: Yosys (and hopefully nextpnr) on Cyclone FPGAs - https://github.com/ZirconiumX/mistral - logs: https://freenode.irclog.whitequark.org/prjmistral
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<jevinskie[m]> Anyone try HAL? I’m wondering how much RE pain is left after you get a netlist
<Lofty> HAL?
<Lofty> Huh.
<daveshah> I chatted a bit with one of its developers late last year who was working on icebox_vlog integration, to RE the bitstream from a certain consumer product
<jevinskie[m]> I know, I should try throwing one of my old college FPGA projects in it and see if I can recognize anything. :)
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