Lofty changed the topic of #prjmistral to: Project Mistral: Yosys (and hopefully nextpnr) on Cyclone FPGAs - https://github.com/ZirconiumX/mistral - logs: https://freenode.irclog.whitequark.org/prjmistral
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<Sarayan> Lofty, I'm going to need your help on timings. I have a lot of information but I'm not entirely sure how it's supposed to be used. And the problem is that I don't see how I could try to reproduce what quartus does simply because I don't know how to have it give me useful information. Do you know how to get delays on a given path, this kind of stuff?
<Sarayan> I don't have the energy available to really try to understand how to use quartus in that area
<Lofty> Sarayan: so, my usual approach is to open up the timing analyser on a design, and there's then an option to show the critical paths. That actually lets you choose things like critical paths through a wire, and also shows you the equivalent TCL command
<Sarayan> ok, let's try that
<Sarayan> first I recompile so that everything is in sync
<Sarayan> ok, timing analyzer open, I need to create a timing netlist I guess?
<Sarayan> and then I'm lost
<Sarayan> Each time I'm trying to get info on a path I'm getting "nothing to report"
<Sarayan> og.kervella.org/mini.zip is the design I use
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<Sarayan> ok report_timing -show_routing -file t seems to give interesting information
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