Lofty changed the topic of #prjmistral to: Project Mistral: Yosys (and hopefully nextpnr) on Cyclone FPGAs - https://github.com/ZirconiumX/mistral - logs: https://freenode.irclog.whitequark.org/prjmistral
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<Sarayan> oh great, for some reason I can't compile the NES core anymore, and jotego's cps1 not happy either
<hansfbaier1> Sarayan: Are those testcases for prjmistral? How cool!!!! <3
<Sarayan> not yet
<Sarayan> they're test cases that put the fpga in interesting (as in varied) configurations to see what is what
<hansfbaier1> Sarayan: In the medium term I want to port some cores over to my arrow SocKit
<hansfbaier1> Sarayan: I see
<hansfbaier1> terasic probably was a bit surprised when the retro gamer community hit their shelves
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<Sarayan> oh, nes compiled after an update
<Sarayan> Lofty, here you go. The LAB is a lot more documented now
<Lofty> Sarayan: thanks!
<Sarayan> hmmm, miage boundaries problem
<Sarayan> image
<Sarayan> fixed
<Sarayan> it's big, hairy and complicated
<Lofty> I think it needs a bit of colour
<Sarayan> There's blue and green :-)
<Lofty> Not what I meant, and you know that :P
<Sarayan> green meaning internal signal
<Sarayan> I thikn what it would really need is interactivity, light up a line when you're hovering over it
<Sarayan> but it's not something I'd know how to do in such a setup
<Lofty> Yeah, but if the wires were also green, it'd be a lot easier to trace them through the ratsnest
<Sarayan> rather than blue? not sure what if would change
<Lofty> They'd be distinct from the other blue wires
<Sarayan> the svgs are in there, they're made under inkscape, convince me! :-)
<Sarayan> I'm using "save a copy" to make the pdf
<Sarayan> The NES doesn't trigger a L7 with feedback, that's why the corresponding mode blocks are empty
<Lofty> Ah
<Lofty> I was just about to ask!
<Sarayan> I am... not unhappy with the result
<Sarayan> I suspect mode is splittable, but having the l7+fb patterns would be necessary to be sure
<Sarayan> having fun with the svgs?
<Lofty> Sarayan: I haven't touched them yet; been trying to fix a yosys bug as part of my job :P
<Sarayan> oh
<Sarayan> yeah, that takes priority
<Sarayan> ok, carry and share chains documented now, I think we have everything that's actually used in there
<Sarayan> (regscan and dft go figure what it is)
<daveshah> dft=design for test
<daveshah> regscan sounds like scan chains as part of that
<Sarayan> oh?
<Sarayan> probably
<Sarayan> Did you see the lab schema?
<daveshah> no, not yet
<daveshah> fancy
<Sarayan> I *think* it's correct except some some weirdnesses in the common block between clock enables, sync clear and sync load
<Sarayan> I wonder if I should try to map the dmf tables on that schema
<Sarayan> wow they're weird
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<Sarayan> fuck, looks like I lost my copy of quartus 9.0
<Sarayan> damn
<etrig> is it not possible to download archived copies any more?
<etrig> I downloaded 4.2 somewhat recently
<etrig> oh no "This version of Quartus II software will no longer be available after 6/26/2020."
<Sarayan> yeah
<etrig> Sarayan: I have 90_quartus_linux.tar and 90sp2_quartus_linux.tar
<Sarayan> I'm interested :-)
<etrig> one moment
<etrig> slowly uploading
<Sarayan> cool
<Sarayan> much thanks, I'll try not to delete it by mistake this time :-)
<etrig> I'll be backing up everything I have just in case :)
<Sarayan> yeah, intel won't give it to you again
<kc8apf> etrig: thanks! I'm trying to build an archive for both Altera and Xilinx
<etrig> kc8apf: I also have: quartusii_40_linux.tar.gz, quartusii_42_linux.tar, quartusii_42_pc.zip, quartusii_42_unix_device_info.tar, Quartus-14.1.0.186-linux-complete.tar
<kc8apf> I'll take whatever you've got. My altera archive is much weaker than Xilinx
<etrig> I'm also looking for anything I can find about the original nios
<etrig> became nearly impossible after intel acquisition
<etrig> kc8apf: transferring everything and then I'll drop a link with file names and hashes
<kc8apf> when was NIOS introduced?
<etrig> 2001, I believe
<kc8apf> I have a few Altera Digital Library ISOs
<etrig> there were some example nios projects included with altera's "processor portfolio," and I only managed to find one release of it on a random south korean ftp site
<kc8apf> I have a NIOS datasheet
<etrig> kc8apf: thanks
<mwk> hmm
<mwk> while we're on subject of archives, does someone have really old ISE versions (like older than on the website, with xc3000/xc5200 support), or XACTstep?
<kc8apf> yes
<kc8apf> I have XACT v5.0, v5.1, v5.2, and v6.0
<etrig> oldest I have is Xilinx_ISE_DS_Lin_12.2_M.63c.1.1.tar
<kc8apf> ISE 4.2, 5.2
<kc8apf> Foundation 1.3, 1.4, 1.5, 2.1
<mwk> I don't know what ISE I'd be interested in, but I do have 4.2
<mwk> [it's on the website]
<mwk> ohh, the early foundations would be interesting
<mwk> and the xacts
<kc8apf> 1.3, Alliance 1.5, 2.1, 3.1, 3.3
<kc8apf> I don't have a great place to upload all these
<etrig> kc8apf: oh, here's the embedded processor portfolio: http://altera.co.kr/_altera/html/_excalibur/
<etrig> includes the isa reference for the 16 and 32-bit memory variants
<kc8apf> just found Quartus II 1.1 ;)
<etrig> and there's even a toolchain at http://cdk4nios.sourceforge.net/
<mwk> hmm, I can set up sftp
<kc8apf> this CD layout is a mess
<kc8apf> rmnios.pdf is the reference manual
<kc8apf> probably what you want most
<etrig> thanks, there's probably a bit of overlap in what I have but it's good to get as much as possible
<Sarayan> hmmm, with any lyck I may be able to get routing delays faster than I expected
<Sarayan> it seems... simpler than I thought
<Sarayan> Anyone knows what "wire fragging" means in a routing timing context?
<daveshah> It could be splitting wires up into smaller RC chunks but that's pretty much a guess
<Sarayan> yeah, can be that
<Sarayan> it has things like gaps_between_tap_points
<Sarayan> where the taps are, I guess, connections with drivers of other wires
<daveshah> That sounds likely yeah
<etrig> kc8apf: just finished, you can replace path with any of the filenames here: https://vx.si/fpga/sha256sums.txt
<etrig> kicking myself for not grabbing more before they disappeared