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<Sarayan>
Happy new years
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<Lofty>
Sarayan: happy end of 2020 at least
<Sarayan>
it's very ended for europe in any case :-)
<Sarayan>
do you know a way to explore python structures?
<Sarayan>
as in, if you pick up og.kervella.org/parse_timing_model.py and og.kervella.org/ddb_cyclonev_la_lab-ff-0-1_18_model.ddb.dmp and run one on the other you get at the end of the script in "root" the whole file as recursive python objects
<Sarayan>
and there's a lot in there, I suspect a complete graph representation of the lab
<Lofty>
Sarayan: just use recursion I guess
<Sarayan>
Explore visually I mean
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<Sarayan>
ok, looks like the lab model has 317 notes (that includes all ten labcells)
<Sarayan>
nodes
<daveshah>
Is this a spice model of the lab?
<Sarayan>
could be
<Sarayan>
just starting to undertand the structure
<Sarayan>
any idea what "unate" can mean? Used as in "unateness", a boolean, and also "pos_unate_paths" and "neg_unate_paths"
<daveshah>
I think it's to do with whether a rising edge can cause a falling edge
<daveshah>
a non-unate can turn a posedge into posedge or negedge
<daveshah>
positive unate posedge into posedge only (or no edge)
<daveshah>
negative unate posedge into negedge only (or no edge)
<Sarayan>
I see
<Sarayan>
obviously useful in edge timing estimation :-)
<daveshah>
yeah, and particularly when a cell is in the clock path
<Sarayan>
interestingly they don't seem to distinguish clock from not
<Sarayan>
only x influences y
<daveshah>
I mean unateness of arcs is particularly important when there is a clock port downstream of those arcs
<daveshah>
for example if you had an inverter (negative unate) in the clock path, then you now have an inverted clock to deal with
<Sarayan>
damn, weird organization, some stuff is structured, some stuff is flat, what the hell intel?
<Sarayan>
aha! you have timing blocks on the boundaries of switchable behaviours
<Lofty>
That's interesting
<Sarayan>
ok, so they have instances (73 of them), to each a block is associated (blocks can be shared)
<Sarayan>
the block has modes, which match muxes or groups of muxes states
<Sarayan>
blocks also have inputs and outputs with pin id. A pin is characterized by the pin id *and* the instance
<Sarayan>
ohhh, and here are the names of the instances