Lofty changed the topic of #prjmistral to: Project Mistral: Yosys (and hopefully nextpnr) on Cyclone FPGAs - https://github.com/ZirconiumX/mistral - logs: https://freenode.irclog.whitequark.org/prjmistral
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<jevinskie[m]> Lofty: you can see my ugly reversing of it here https://gist.github.com/jevinskie/a4ed8a6337e791a07b412a5be9f132af
<Lofty> Huh, neat
<jevinskie[m]> You can see I was struggling with the weird (for me) bit endianness so you see leftover debug stuff like a null shuffle `(n0, n1, n2, n3) = (n0, n1, n2, n3)`
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