Lofty changed the topic of #prjmistral to: Project Mistral: Yosys (and hopefully nextpnr) on Cyclone FPGAs - https://github.com/ZirconiumX/mistral - logs: https://freenode.irclog.whitequark.org/prjmistral
<Sarayan> ;5A;5A/jmi
<Sarayan> gah
<Sarayan> oh wow
<Sarayan> it seems like the 8236 bits are optional inverters
<daveshah> Seems very plausible
<Sarayan> associated to that many routing->block connections
<Sarayan> I have the table of the connection points
<Sarayan> plus the name of the connections, and they match
<Sarayan> I guess RPI = Routing Port Inverter or something of th kind
<Sarayan> Programmable
<Sarayan> Routing Programmable Inverter I my current guess
<Sarayan> ok, number of incorrect bits went from ~1000 to ~100 by adding the inverters, good. The rest may just be typos, too
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