Lofty changed the topic of #prjmistral to: Project Mistral: Yosys (and hopefully nextpnr) on Cyclone FPGAs - https://github.com/ZirconiumX/mistral - logs: https://freenode.irclog.whitequark.org/prjmistral
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<Sarayan> does "RPI", designating a configuration bit type, mean anything to anyone?
<mwk> ... raspberry pi compatibility mode for the FPGA
<mwk> [no, not really]
<Sarayan> (I hope not)
<Sarayan> (there's a lot of them in the HPS interface, do you think the sx120f embeds a pi?)
<mwk> hmmm
<Sarayan> I'm kind of amused by the asmdb stuff though
<Sarayan> there a lot of "here is the routing table, all in cram, here are the in-cram tiles, with perfect rectangles disjoint from the routing, here are the peripheral blocks, in pram"
<Sarayan> and then there's "here's a bunch of bits in the cram that are used, they're numbered 0 to 2172, enjoy"
<Sarayan> 3172 sorry
<Sarayan> the hps interface configuration seems to be entirely build from "here are bits, enjoy"
<mwk> you're still at the "looking for reason" stage here, aren't you
<Sarayan> sometimes
<mwk> cannot recommend it
<Sarayan> indeed
<Sarayan> these bits have amusing side effects
<Sarayan> for instance using partial reconfiguration you can't reconfigure which clock network is driven from what
<Sarayan> but it seems to you *can* invert it
<Sarayan> becaues the inversion flag is in cram and all the rest in pram
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