Lofty changed the topic of #prjmistral to: Project Mistral: Yosys (and hopefully nextpnr) on Cyclone FPGAs - https://github.com/ZirconiumX/mistral - logs: https://freenode.irclog.whitequark.org/prjmistral
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<Sarayan> somehow, a grep in a 31G file takes a little time
<Lofty> Sarayan: ripgrep!
<Sarayan> well, it's done
<Sarayan> it's getting interesting
<Lofty> Oh?
<Sarayan> quartus sets bits in the cram that are not part of the routing and no part of a BEL tile
<Sarayan> need to find out what triggers it
<Lofty> Mmm
<Sarayan> But at least it's not set by fmaker because it's not in any table, not because I fucked one
<Sarayan> process_cdb end_of_phase
<Sarayan> that doesn't help much, damn
<daveshah> how many bits are we talking about?
<daveshah> sometimes 'spare' bits are used for error correcting codes
<daveshah> e.g. Xilinx put them somewhere in the middle of the frame
<Sarayan> 1016 bits
<Sarayan> There are ECCs, I'm generating them already though
<Sarayan> that goes through the "object instanciation" path
<Sarayan> well, just after, it seems
<Sarayan> hmmm yeah, some stuff (need to find out what) can collate bits to set at the end
<Sarayan> hmmmm, seems to have something to do with gpio
<Sarayan> I guess gpio has both bits in cram and pram
<Sarayan> no sure where they setup the cram ones though
<Sarayan> need to look :-)
<Sarayan> ah no, that's just the support to asmio_dump_model
<Sarayan> ohhhh, magic code to ensure all clock networks are driven
<Sarayan> probably connects the unused ones to ground
<Sarayan> somehow
<Sarayan> ok, I found where the bitmap is hiding
<Sarayan> it's about output enable invert and data invert
<Sarayan> oh my, but of course there's a fuckload of this waeirdly defined bits
<Sarayan> I am joy