Lofty changed the topic of #prjmistral to: Project Mistral: Yosys (and hopefully nextpnr) on Cyclone FPGAs - https://github.com/ZirconiumX/mistral - logs: https://freenode.irclog.whitequark.org/prjmistral
<chipb> uh, yeah.
<chipb> you might want to take a look at the "preloader" source.
<chipb> sadly, it builds with a chunk of data that comes from quartus output. I can't remember if that clock setup is in the opaque data or not.
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