Lofty changed the topic of #prjmistral to: Project Mistral: Yosys (and hopefully nextpnr) on Cyclone FPGAs - https://github.com/ZirconiumX/mistral - logs: https://freenode.irclog.whitequark.org/prjmistral
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<rombik_su> Lofty: Sorry, it's been awhile, but here's my die mapping results: https://github.com/wirebond/catapult_v2_pikes_peak/wiki/test
<rombik_su> SKUs is a bit messed up, GX series got those 'Base', 'Mainstream' and 'Extended features' variants, so I decided to go for model names from family overview table if you don't mind
<rombik_su> I've got my Arria V GX devkit with 5AGXFB3H4F35C4N in it, which is arriavd3 die. Since it's the same IDCODE as GT variant with the same die, I can try to load bitstream from a different device.
<rombik_su> I wonder if you can unlock 10 Gb/s XCVRs in GX variant
<Sarayan> 5AGXA7 is probably arriav7, not v3
<Sarayan> 5AGTD7 is probably arriavd7
<rombik_su> Sarayan: yup, did a typo with 5AGXA7; will re-check 5AGTD7
<Sarayan> oh yeah, the b3/d7 relationship is strange
<rombik_su> Sarayan: Nope, Quartus reaching for arriavb7 files for GTD7 compilation
<Sarayan> there is no d7 nor b3 I guess?
<rombik_su> That's correct, we have only those: arriava3, arriava7, arriavb3_es (no hits so far), arriavb7, arriavd3 and arriav_soc_b5
<rombik_su> There's a bunch of ES and/or hidden devices in the database btw
<rombik_su> I blame Gregg for that
<rombik_su> (for all the mess in die-to-SKU relations)
<Sarayan> yeah, it's his fault I'm sure
<rombik_su> Since it's the only person we know of
<Sarayan> Isn't there a second?
<Sarayan> I vaguely seem to remember
<rombik_su> There's also Mike and Greta, but neither of those names got the right amount of consonants to be a EDA supervillain
<Sarayan> ahhhhhh
<Sarayan> they're the miniboss couple
<rombik_su> :D
<Lofty> Morning
<rombik_su> Hi there!
<Lofty> Should I put this in the Mistral wiki page? :p
<rombik_su> Lofty: I'll push it, I was waiting for your approval
<Lofty> Well, it looks good to me!
<Lofty> I did combine all the models by family, but maybe this approach makes more sense
<rombik_su> I can modify it if you say so, no problem, there's about 20 devices in this family, my idea is that it would be a bit easier to read if it will be divided by sub-families
<rombik_su> Lofty: ^
<Lofty> Yeah, I do think you're right
<rombik_su> Damn it, there's no PRs for wiki pages on GitHub : /
<rombik_su> Lofty: I can't find any straightforward ways to PR/push my updates to your repo. Do you know a good way to do that?
<Lofty> Just edit the wiki page :P
<rombik_su> Right on the Github page? I don't have 'Edit' button.
<Lofty> Now you do
<rombik_su> Lofty: Thanks, done!
<Lofty> You're welcome
<rombik_su> Lofty: Everything alright with A5 dump? Can I nuke it on my machine?
<rombik_su> I need to make space for S5 device files to investigate the difference between A5GZ and S5 files )
<Lofty> rombik_su: sure, although I don't have nearly enough space on my disk to store it as anything other than the archive :P
<rombik_su> Yup, same story here
<Lofty> But yeah, sure
<Sarayan> which chip are you studying, arria V?
<Sarayan> I want to RE it?
<Sarayan> sorry
<Sarayan> You want to RE it?
<rombik_su> I'm just poking around A5, I'm not nearly smart enough to RE it
<rombik_su> I'm looking at the floorplan for both A5GXB3 (6 Gbps) and A5GTD3 (10 Gbps, both sharing arriavd3 die); looks GT version uses the same XCVR tile. Also, IP generator for transceiver PHY let you set 10G speed on both GX and GT device for some reason.
<rombik_su> A5GX took A5GT bitstream like a champ btw
<rombik_su> So probably the difference there is just a binning and maybe I can run GX version on a GT speed
<Lofty> rombik_su: Thanks for this, by the way
<rombik_su> For what?
<Lofty> The Arria V dumps, checking bitstreams on your hardware, ...
<rombik_su> Oh, don't mention
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