Lofty changed the topic of #prjmistral to: Project Mistral: Yosys (and hopefully nextpnr) on Cyclone FPGAs - https://github.com/ZirconiumX/mistral - logs: https://freenode.irclog.whitequark.org/prjmistral
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<Sarayan> ok, at this point the main missing inputs/outputs are the plls
<Sarayan> and I need to overhaul the cff management, it doesn't work anyway
phiren is now known as phire