Lofty changed the topic of #prjmistral to: Project Mistral: Yosys (and hopefully nextpnr) on Cyclone FPGAs - https://github.com/ZirconiumX/mistral - logs: https://freenode.irclog.whitequark.org/prjmistral
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<Sarayan> damn, half the i/o goes through the hmcphy
<daveshah> hard memory controller?
<daveshah> tbf, half the IO of a typical FPGA design are usually memory...
<Sarayan> yeah
<Sarayan> but it's used as random gpio
<Sarayan> e.g. the power led is on IOINTDQDOUT 168
<Sarayan> whatever that is :-)
<Sarayan> and the damn phy uses 1321 input and 598 output connections to the routing grid
<Sarayan> it's big-ass crap
<Lofty> Ouch
<Sarayan> github is up-to-date
<Sarayan> I think I'm handling the cff incorrectly, the gpio configuration doesn't decode correctly
<Lofty> Damn, you *have* been busy
<Sarayan> fixed some stuff in the routing
<Sarayan> right now I'm trying to identify everything that at the border of the routing in the NES rbf
<Sarayan> but, well, fmaker decomp is slowly going somewhere
<Sarayan> I aim to be able to do a decomp/comp cycle, but I'm not anywhere near it yet :-)
<Sarayan> Now did I manage to find that phy's doc
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