Lofty changed the topic of #prjmistral to: Project Mistral: Yosys (and hopefully nextpnr) on Cyclone FPGAs - https://github.com/ZirconiumX/mistral - logs: https://freenode.irclog.whitequark.org/prjmistral
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<Sarayan> Lofty, did you see anything talking about "Orphan PLL"?
<Lofty> Nope?
<Sarayan> ok, that's the name of some inputs of some of the clock muxes
<Sarayan> go figure
<Lofty> PLLs feeding into the clock network makes sense
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