Lofty changed the topic of #prjmistral to: Project Mistral: Yosys (and hopefully nextpnr) on Cyclone FPGAs - https://github.com/ZirconiumX/mistral - logs: https://freenode.irclog.whitequark.org/prjmistral
<trabucayre> I assume it's only new for me. data area for pof, rbf svf and rpd is the same
<Sarayan> I haven't managed to make the rbf format change even when changing the programming mode
<Sarayan> so I guess it's really fixed
<trabucayre> ok
<trabucayre> the good thing (for me) is to have access to a format less boring than svf
<Sarayan> rbf has the fpga firmware and nothing else whatsoever
<trabucayre> Sarayan: yep. But with commands seen in an svf file I've enough to program my fpga
<Sarayan> ah cool
<trabucayre> I regret only to don't have access to status register to avoid stupid wait...
<trabucayre> my cycloneV is well programmed with rbf
<trabucayre> In fact pof is easy to parse too (really near xilinx .bit file)
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