Lofty changed the topic of #prjmistral to: Project Mistral: Yosys (and hopefully nextpnr) on Cyclone FPGAs - https://github.com/ZirconiumX/mistral - logs: https://freenode.irclog.whitequark.org/prjmistral
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<Sarayan> Anyone has a clue about what IR_FIFO_USERDES is? It seems to be intimately linked to the io blocks
<daveshah> IO blocks sometimes have a FIFO for going between DQS domain and fabric
<daveshah> SERDES in this context probably isn't the fancy transceivers but the simple 4:1/8:1/whatever gearing on the regular IO pins
<Sarayan> Ohhhh, I fixated on USER and missed SERDES
<Sarayan> thanks :-)