Lofty changed the topic of #prjmistral to: Project Mistral: Yosys (and hopefully nextpnr) on Cyclone FPGAs - https://github.com/ZirconiumX/mistral - logs: https://freenode.irclog.whitequark.org/prjmistral
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<Sarayan> sure, but "orphan"?
<Sarayan> I wonder if it means "one that does not have a dedidated clock pin input"
<Sarayan> should check where it's coming from mind you
<Sarayan> FF_PLL_RE_PLLCOUT.00.00.00.0004 - CLKBUF_CLUSTER_RE_CORNER_PLL_C.05.00.00.0003 CLKBUF_CLUSTER_RE_ORPHAN_PLLB_C0.00.35.03.0001 CLKBUF_CLUSTER_RE_ORPHAN_PLLT_C0.00.35.03.0001 CLKBUF_CLUSTER_RE_PLLCENTERA_C.42.00.00.0004
<Sarayan> FF_PLL_RE_PLLCOUT.00.73.00.0004 - CLKBUF_CLUSTER_RE_CORNER_PLL_C.05.81.00.0003 CLKBUF_CLUSTER_RE_ORPHAN_PLLB_C0.00.35.03.0000 CLKBUF_CLUSTER_RE_ORPHAN_PLLT_C0.00.35.03.0000 CLKBUF_CLUSTER_RE_PLLCENTERA_C.42.81.00.0004
<Sarayan> counter 4 of two of the plls, go figure
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