Lofty changed the topic of #prjmistral to: Project Mistral: Yosys (and hopefully nextpnr) on Cyclone FPGAs - https://github.com/ZirconiumX/mistral - logs: https://freenode.irclog.whitequark.org/prjmistral
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<jevinskie[m]> Orphan PLL == phantom PLL in the bitstream?
<jevinskie[m]> Ah I missed the answer :)
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<Sarayan> Damn, the hps is around 600 signals
<Sarayan> counting as one when it's more than single-bit wide too
<Lofty> Oh lord
<Lofty> Sarayan: I guess you can just ignore it for now
<Sarayan> well, it's used kind of a lot in mister
<Lofty> Sure, but without it being plugged into nextpnr it's probably not going to achieve much.
<Sarayan> that's your job :-P
<Lofty> Sure, but since you've done all the reverse engineering so far I have no idea what the bitstream looks like
<Sarayan> Oh that has not much influence on the bitstream
<Sarayan> it's "easy"
<Sarayan> the bitstream is in three parts: options, cff, cram
<Sarayan> options is that, options. 32 spans of 40 bits, 18 of them or so that are not actually used, with things like programming voltages, jtag, etc
<Sarayan> cff is a vector of bits which program every function block that is not lab, mlab, dsp or m10k
<Sarayan> cram is a rectangle of bits with lab, mlab, dsp and m10k plus all of the routing
<Sarayan> only cram is compressed incidentally, and if I understood correctly it's the only one encrypted too
<Sarayan> routing is a bunch of n:1 muxes which, for most of them, have also an "off" position
<Sarayan> maximum count of bits is 18, maximum number of entries is 44
<Sarayan> one specific node type, DCMUX, is a one-bit two entries mux, which selects between data and clock on a lot of clock-like block inputs
<Sarayan> the boundaries of the routing are GIN/GOUT, generic data in/out, GCLK/RCLK/PCLK/GCLKFB/RCLKFB which are driven by clock muxes blocks and HSSI, LCMUX and in some cases TCLK as clock inputs to blocks
<Sarayan> in the library I have routing nodes (rnode_t) which are nodes in the routing grid, and port nodes (pnode_t) which are ports of the blocks, and calls to get the rnode connected to a pnode and back
<Sarayan> so you configure the blocks, and you find the routing nodes matching the block ports, and configure the routing muxes
<Sarayan> right now I'm trying to identify all the boundary nodes of NES.rbf
<Sarayan> fmaker routes2 will given you all the connections with unidentified boundaries
<Sarayan> mini has all its routes identified, that gives:
<Sarayan> CMUXVG.042.000.2:CLKOUT IO.089.009.0:CLKIN_OUT.0
<Sarayan> CMUXVG.042.000.2:CLKOUT LAB.088.009:CLKIN.0
<Sarayan> IO.089.008.1:DATAOUT.0 LAB.088.009.0:A
<Sarayan> LAB.088.009.0:FFT0 IO.089.009.0:DATAIN.0
<Sarayan> IO.089.009.2:DATAOUT.1 LAB.088.009.0:B
<Sarayan> the clk input pin -> clock mux link is dedicated, so it doesn't show up there
<Sarayan> and it's not even there in the tables yet :-)